...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>Journal of Electronic Packaging >Experimental Characterization of the Vertical and Lateral Heat Transfer in Three-Dimensional Stacked Die Packages
【24h】

Experimental Characterization of the Vertical and Lateral Heat Transfer in Three-Dimensional Stacked Die Packages

机译：三维堆叠模具封装中纵向和横向传热的实验表征

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

In this paper, we present the experimental characterization of three-dimensional (3D) packages using a dedicated stackahle test chip. An advanced complementary metal oxide silicon (CMOS) test chip with programmable power distribution has been designed, fabricated, stacked, and packaged in molded and bare die 3D packages. The packages have been experimentally characterized in test sockets with and without cooling and soldered to the printed circuit board (PCB). Using uniform and localized hot spot power distribution, the thermal self-heating and thermal coupling resistance and the lateral spreading in the 3D packages have been studied. Furthermore, the measurements have been used to characterize the thermal properties of the die-die interface and to calibrate a thermal model for the calculation of equivalent properties of underfilled μbump arrays. This model has been applied to study the tradeoff' between the standoff height reduction and the underfill thermal conductivity increase in order to reduce the interdie thermal resistance.
机译：在本文中，我们介绍了使用专用stackahle测试芯片对三维（3D）封装进行的实验表征。已经设计，制造，堆叠和封装了模制和裸芯片3D封装中的，具有可编程功率分配的高级互补金属氧化物硅（CMOS）测试芯片。该封装已在带有和不带有冷却功能的测试插座中进行了实验表征，并焊接至印刷电路板（PCB）。使用均匀且局部的热点功率分布，研究了3D封装中的热自发热和热耦合电阻以及横向扩散。此外，这些测量已用于表征管芯-芯片界面的热性能，并用于校准热模型，以计算未填充μbump阵列的等效性能。该模型已被用于研究支座高度减小与底部填充热导率增加之间的权衡，以减小模间热阻。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号