...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>Microelectronics reliability >Structural design optimization for board-level drop reliability of wafer-level chip-scale packages
【24h】

Structural design optimization for board-level drop reliability of wafer-level chip-scale packages

机译：晶圆级芯片级封装的板级跌落可靠性的结构设计优化

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

In this paper, the Taguchi optimization method is applied to obtain the optimal design in enhancing board-level drop reliability of a wafer-level chip-scale package (WLCSP) under JEDEC drop test condition B, which features a half-sine impact acceleration pulse with a peak acceleration of 1500 G and a pulse duration of 0.5 ms. An L_9 (3~4) orthogonal array is arranged for the optimization of four control factors that involve compositions of solder alloys and thickness of die and polyimide passivation layers. The submodeling technique capable of dealing with path-dependent features, including elastoplastic responses of solder joints and structural nonlinearity under drop impacts, is applied so that delicate structures of passivation, under bump metallurgy (UBM), and redistribution line (RDL) in a WLCSP package can be taken into account. Effects of these control factors on the drop reliability of WLCSP are compared and ranked.
机译：本文使用Taguchi优化方法来获得优化设计，以增强JEDEC跌落测试条件B下晶片级芯片级封装（WLCSP）的板级跌落可靠性，该条件具有半正弦冲击加速脉冲峰值加速度为1500 G，脉冲持续时间为0.5 ms。布置L_9（3〜4）正交阵列以优化四个控制因素，这些因素涉及焊料合金的成分以及芯片和聚酰亚胺钝化层的厚度。应用能够处理路径相关特征的子建模技术，包括焊点的弹塑性响应和在跌落冲击下的结构非线性，以便在WLCSP中钝化的精细结构（在凸块冶金（UBM）和重分布线（RDL）下）可以考虑包装。比较并排序这些控制因素对WLCSP跌落可靠性的影响。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号