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首页> 外文期刊>IEEE Transactions on Parallel and Distributed Systems >An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors
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An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors

机译：一种针对多核处理器中最后一级STT-RAM缓存的有效保护技术

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摘要

Due to serious problems of SRAM-based caches in nano-scale technologies, researchers seek for new alternatives. Among the existing options, STT-RAM seems to be the most promising alternative. With high density and negligible leakage power, STT-RAMs open a new door to respond to future demands of multi-core systems, i.e., large on-chip caches. However, several problems in STT-RAMs should be overcome to make it applicable in on-chip caches. High probability of write error due to stochastic switching is a major problem in STT-RAMs. Conventional Error-Correcting Codes (ECCs) impose significant area and energy consumption overheads to protect STT-RAM caches. These overheads in multi-core processors with large last-level caches are not affordable. In this paper, we propose Asymmetry-Aware Protection Technique (A^2 PT) to efficiently protect the STT-RAM caches. A^2 PT benefits from error rate asymmetry of STT-RAM write operations to provide the required level of cache protection with significantly lower overheads. Compared with the conventional ECC configuration, the evaluation results show that A ^2 PT reduces the area and energy consumption overheads by about 42 and 50 percent, respectively, while providing the same level of protection. Moreover, A^2 PT decreases the number of bit switching in write operations by 28 percent, which leads to about 25 percent saving in write energy consumption.
机译：由于纳米技术中基于SRAM的高速缓存存在严重问题，研究人员正在寻找新的替代方法。在现有选项中，STT-RAM似乎是最有前途的选择。 STT-RAM具有高密度和微不足道的泄漏功率，为满足多核系统（即大型片上高速缓存）的未来需求打开了新的大门。但是，应克服STT-RAM中的几个问题，使其适用于片上高速缓存。 STT-RAM中的主要问题是由于随机切换而引起的高写入错误概率。常规纠错码（ECC）施加了很大的面积和能耗开销，以保护STT-RAM缓存。具有大型最后一级缓存的多核处理器中的这些开销是无法承受的。在本文中，我们提出了不对称感知保护技术（A ^ 2 PT）以有效保护STT-RAM缓存。 A ^ 2 PT受益于STT-RAM写操作的错误率不对称性，从而以较低的开销提供所需的缓存保护级别。与传统的ECC配置相比，评估结果表明，A ^ 2 PT可以在提供相同级别的保护的同时分别减少约42％和50％的能耗开销。此外，A ^ 2 PT将写操作中的位切换次数减少了28％，从而节省了约25％的写能耗。

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