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首页> 外文期刊>Power Electronics, IET >Design of high-speed gate driver to reduce switching loss and mitigate parasitic effects for SiC MOSFET
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Design of high-speed gate driver to reduce switching loss and mitigate parasitic effects for SiC MOSFET

机译：降低SiC MOSFET的开关损耗并减轻寄生效应的高速栅极驱动器设计

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摘要

The high switching speed in a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) will aggravate the parasitic effects (d/d and d/d) arising from the interaction with parasitic elements. In this project, a high-speed gate driver has been developed and optimised for the commercially available SiC MOSFET power module. The impact of various parasitic parameters on parasitic effects is initially evaluated. Then, an improved gate-assisted circuit is proposed with a local low-impedance path for both discharging and dd currents. It allows maximised turn-off speed (d/d up to 36 Vs) and minimised turn-off loss (reduction up to 70%). It also produces a reduction in electromagnetic interference. The gate voltage spike due to dd current is reduced below the threshold voltage at various testing conditions.
机译：碳化硅（SiC）金属氧化物半导体场效应晶体管（MOSFET）中的高开关速度将加剧由与寄生元件的相互作用引起的寄生效应（d / d和d / d）。在该项目中，已经开发出了高速栅极驱动器并针对商用SiC MOSFET电源模块进行了优化。首先评估各种寄生参数对寄生效应的影响。然后，提出了一种改进的栅极辅助电路，该电路具有用于放电和dd电流的局部低阻抗路径。它允许最大关断速度（d / d最高36 V / ns）和最小关断损耗（最大降低70％）。它还可以减少电磁干扰。在各种测试条件下，由于dd电流引起的栅极电压尖峰降低到阈值电压以下。

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