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A hardware/software development environment for SoC-based time interval counters

机译：基于SoC的时间间隔计数器的硬件/软件开发环境

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摘要

The paper describes a design environment for development of precise time counters. The design was implemented in a System-on-Chip Zynq from Xilinx as an embedded solution with a custom user interface. The paper presents the system design, a dedicated time counter interface, and software running on the processing part of the Zynq device. It also contains the results of all system performance tests. The tests reveal the design advantages over the traditional approach, involving an FPGA device connected to a PC that serves as a host with a dedicated user interface. The presented development environment allowed reducing the calibration and measurement times twofold and threefold, respectively. Furthermore, thanks to the bus interface designed for data transmission from the time counter to the control module, the 200 MB/s data throughput inside the SoC was achieved.
机译：本文介绍了用于开发精确计时器的设计环境。该设计是在Xilinx的片上系统Zynq中实现的，作为具有自定义用户界面的嵌入式解决方案。本文介绍了系统设计，专用的计时器接口以及在Zynq设备处理部分运行的软件。它还包含所有系统性能测试的结果。测试揭示了与传统方法相比的设计优势，传统方法涉及将FPGA器件连接到PC，该PC用作具有专用用户界面的主机。提出的开发环境可以分别将校准和测量时间减少两倍和三倍。此外，由于总线接口设计用于从时间计数器到控制模块的数据传输，因此在SoC内部实现了200 MB / s的数据吞吐量。

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