Noise analysis methodology for partially depleted SOI circuits

Nanua M.; Blaauw D.

首页> 外文期刊>IEEE Journal of Solid-State Circuits >Noise analysis methodology for partially depleted SOI circuits

【24h】

Noise analysis methodology for partially depleted SOI circuits

机译：部分耗尽SOI电路的噪声分析方法

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相似文献
相关主题

摘要

In partially depleted silicon-on-insulator (PD-SOI) technology, signal switching history and intial state of the circuit nodes can affect the device body voltage and also cause parasitic BJT leakage currents, which can lead to significant increase in noise propagation and noise failures. In this brief we explore the effects of input switching history, initial circuit conditions and the parasitic BJT device on all steps in a traditional noise analysis methodology: noise injection, noise propagation, and noise failure criterion. We present a new noise analysis methodology to account for the floating body and the BJT effects in PD SOI technology. We demonstrate the new technique on an industrial microprocessor design in PD SOI and show that the current noise analysis methods do not account for 56% of noise fails.

机译：在部分耗尽的绝缘体上硅（PD-SOI）技术中，信号切换历史和电路节点的初始状态会影响器件本体电压，并导致寄生BJT泄漏电流，从而导致噪声传播和噪声显着增加。失败。在本文中，我们探讨了输入开关历史，初始电路条件和寄生BJT器件对传统噪声分析方法中所有步骤的影响：噪声注入，噪声传播和噪声故障准则。我们提出了一种新的噪声分析方法，以解决PD SOI技术中的浮体和BJT效应。我们在PD SOI的工业微处理器设计上演示了这项新技术，并表明当前的噪声分析方法无法解决56％的故障噪声。

著录项

来源
《IEEE Journal of Solid-State Circuits》 |2004年第9期|p.1581-1585|共5页
作者
Nanua M.; Blaauw D.;
展开▼
作者单位

展开▼
收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
bipolar transistors; integrated circuit noise; leakage currents; silicon-on-insulator; BJT leakage currents; circuit nodes; device body voltage; industrial microprocessor design; initial circuit conditions; noise analysis; noise failure criterion; noise injection; n;

机译：双极晶体管;集成电路噪声;漏电流;绝缘体上硅;BJT漏电流;电路节点;器件本体电压;工业微处理器设计;初始电路条件;噪声分析;噪声破坏准则;噪声注入;n;

相似文献

外文文献
中文文献
专利

1. 0.25 μm fully depleted SOI MOSFETs for RF mixed analog-digital circuits, including a comparison with partially depleted devices with relation to high frequency noise parameters [J] . M. Vanmackelberg, C. Raynaud, O. Faynot Solid-State Electronics . 2002,第3期

机译：0.25μm全耗尽SOI MOSFET，用于RF混合模拟数字电路，包括与部分耗尽器件的高频噪声参数相关的比较
2. Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology [J] . Chan S.C., Shepard K.L., Dae-Jin Kim IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2002,第8期

机译：部分耗尽绝缘体上硅技术中数字集成电路的静态噪声分析
3. Simulation of partially and near fully depleted SOI MOSFET devices and circuits using SPICE compatible physical subcircuit model [J] . Mohamed A. Imam, Mohamed A. Osman, Ashraf A. Osman Microelectronics & Reliability . 2004,第1期

机译：使用兼容SPICE的物理子电路模型仿真部分和接近完全耗尽的SOI MOSFET器件和电路
4. Noise analysis methodology for partially depleted SOI circuits [C] . Nanua, M., Blaauw, . 2003

机译：部分耗尽SOI电路的噪声分析方法
5. Radiation-hardened analog circuits in partially-depleted SOI CMOS. [D] . Perez, Alfredo. 2005

机译：部分耗尽的SOI CMOS中的辐射硬化模拟电路。
6. Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors [O] . Xiaoliang Ge, Albert J. P. Theuwissen 2018

机译：CMOS图像传感器的电荷域采样读出电路的时间噪声分析
7. Static Noise Analysis for Digital Integrated Circuits in Partially Depleted Silicon-on-Insulator Technology [O] . Steven C. Chan, Student Member, Kenneth L. Shepard, 2002

机译：部分耗尽硅绝缘子技术中数字集成电路的静态噪声分析

Noise analysis methodology for partially depleted SOI circuits

摘要

著录项

相似文献

相关主题

期刊订阅