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Design and Performance Evaluation of Schmitt Trigger for Nanoscale CMOS

机译：纳米CMOS施密特触发器的设计与性能评估。

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摘要

The CMOS device is used to achieve better performance in terms of speed, power dissipation, size, reliability and hysteresis. Schmitt trigger minimized power consumption and improving compatibility with low voltage power supplies and analog component the most effective solution is to reduce the power consumption. This paper presented the performance comparison of 6T conventional, and 4T Schmitt trigger is used in such a way that by adjusting its threshold voltage, the signal can be made to increase early, thereby reducing the signal delay also due to less switching time, power dissipation is less, circuit is simulated in cadence in both 180 nm and 45 nm technology, a simulation result show that 4T Schmitt trigger 12.3% delay reduction and 24% power reduction.
机译：CMOS器件用于在速度，功耗，尺寸，可靠性和滞后方面实现更好的性能。施密特触发器可将功耗降至最低，并改善与低压电源和模拟组件的兼容性，最有效的解决方案是降低功耗。本文介绍了传统6T的性能比较，并使用了4T施密特触发器，通过调整其阈值电压，可以使信号尽早增加，从而也减少了切换时间和功耗，从而减少了信号延迟。较小的是，电路在180 nm和45 nm技术中均以节奏进行了仿真，仿真结果表明4T Schmitt触发器可降低12.3％的延迟，降低24％的功耗。

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