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首页> 外文期刊>The International Journal of Advanced Manufacturing Technology >Stress analysis of lead-free solders with under bump metallurgy in a wafer level chip scale package
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Stress analysis of lead-free solders with under bump metallurgy in a wafer level chip scale package

机译：晶圆级芯片规模封装中带有凸点下冶金的无铅焊料的应力分析

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摘要

The wafer level chip scale assembly (WLCSP) has increasingly become popular due to its compact, wafer scale assembly. In a WLCSP assembly, the under bump metallurgy (UBM) connecting the solder joints and the chip is crucial for the assembly reliability. This study focuses on a WLCSP with 96.5Sn3.5Ag/95.5Sn3.8Ag0. 7Cu solder joints and Ti/Cu/Ni UBM on a 2-layer micro via build-up electric board. Furthermore, the Garofalo-Arrhenius creep model in the finite element analysis software ANSYS 6.0 is used for simulations on the WLCSP assembly under thermal cycling to investigate the deformations of the assembly with different thickness of nickel layer, the maximum equivalent strain and maximum equivalent stress of microvias/joints. Finally, the Coffin-Manson equation is applied to predict the fatigue lives of four combinations of solder joints with different eutectic alloy and thickness of nickel layer.
机译：晶圆级芯片级组件（WLCSP）由于其紧凑的晶圆级组件而变得越来越流行。在WLCSP组件中，连接焊点和芯片的凸点下冶金（UBM）对于组件的可靠性至关重要。这项研究的重点是具有96.5Sn3.5Ag / 95.5Sn3.8Ag0的WLCSP。在2层微孔板上堆积7Cu焊点和Ti / Cu / Ni UBM。此外，使用有限元分析软件ANSYS 6.0中的Garofalo-Arrhenius蠕变模型对WLCSP组件在热循环下的仿真进行了研究，以研究不同厚度的镍层，最大等效应变和最大等效应力时组件的变形。微孔/接头。最后，使用Coffin-Manson方程来预测具有不同共晶合金和镍层厚度的四种焊点组合的疲劳寿命。

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