CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff

Yuanlin Lu; Vishwani D. Agrawal

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CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff

机译：CMOS泄漏和毛刺最小化，以权衡性能

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A mixed integer linear programming (MILP) technique simultaneously minimizes the leakage and glitch power consumption of a static CMOS circuit for any specified input to output delay. In a dual-threshold design, the number of high-threshold devices is maximized and a minimum number of delay elements are inserted to reduce the differential path delays below the inertial delays of incident gates. The key features of the method are that the constraint set size for the MILP model is linear in the circuit size and power-performance tradeoff is allowed. Experimental results show 96%, 40%, and 70% reductions of leakage power, dynamic power, and total power, respectively, for the benchmark circuit C7552 implemented in the 70 nm BPTM CMOS technology.

机译：对于任何指定的输入到输出延迟，混合整数线性编程（MILP）技术可同时将静态CMOS电路的泄漏和毛刺功耗降至最低。在双阈值设计中，高阈值器件的数量被最大化，并且插入了最小数量的延迟元件，以将差分路径延迟降低到入射门的惯性延迟以下。该方法的关键特征是MILP模型的约束集大小在电路大小上是线性的，并且可以在功率性能之间进行权衡。实验结果表明，采用70 nm BPTM CMOS技术实现的基准电路C7552，泄漏功率，动态功率和总功率分别降低了96％，40％和70％。

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来源
《Journal of Low Power Electronics》 |2006年第3期|共10页
作者
Yuanlin Lu; Vishwani D. Agrawal;
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原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
关键词
Dual-Threshold CMOS Circuits; Dynamic Power; Leakage Reduction; Low Power Design; Glitch-Free Design; Mixed Integer Linear Programming (MILP);

机译：双阈值CMOS电路;动态功率;减少泄漏;低功耗设计;无毛刺设计;混合整数线性编程（MILP）;

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1. CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff [J] . Yuanlin Lu, Vishwani D. Agrawal Journal of Low Power Electronics . 2006,第3期

机译：CMOS泄漏和毛刺最小化，以权衡性能
2. Review of Circuit Level Leakage Minimization Techniques in CMOS VLSI Circuits [J] . Lorenzo Rohit, Chaudhury Saurabh IETE Technical Review . 2017,第2期

机译：CMOS VLSI电路中的电路级漏电最小化技术综述
3. High-efficiency CMOS rectifier with minimized leakage and threshold cancellation features for low power bio-implants [J] . Khan Sadeque Reza, Choi GoangSeog Microelectronics journal . 2017,第auga期

机译：高效的CMOS整流器，具有最小的泄漏和阈值消除功能，适用于低功耗生物植入物
4. Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation [C] . Yuanlin Lu, Vishwani D. Agrawal International Conference on VLSI Design . 2007

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5. Performance tradeoffs of wide-bit CMOS nanometer adder topologies with applied leakage reduction techniques. [D] . Romo, Claudia. 2010

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6. Effect of Contact Plug Deposition Conditions on Junction Leakage and Contact Resistance in Multilevel CMOS Logic Interconnection Device [O] . Yinhua Cui, Jeong Yeul Jeong, Yuan Gao, 2020

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7. Gate triggering: A new framework for minimizing glitch power dissipation in static CMOS ICs and its ILP-based optimization [O] . Nihar R. Mahapatra, Rajagopalan Janakiraman 2008

机译：栅极触发：一个新的框架，用于最小化静态CMOS IC中的毛刺功率耗散及其基于ILP的优化

CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff

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