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首页> 外文期刊>Journal of Low Power Electronics >Robust Low Power Embedded SRAM: From System Considerations to Cell Design
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Robust Low Power Embedded SRAM: From System Considerations to Cell Design

机译：强大的低功耗嵌入式SRAM：从系统考虑到单元设计

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摘要

SRAM will remain important for digital ICs because of its low latency, although it faces strong competition from external DRAM. With the recent attention for "green" products, power reduction in digital systems stays in focus and therefore so does low power SRAM design. For many systems, properly designed SRAM has a low contribution to total SoC power, which means that the significant design effort required for low voltage SRAM does not pay off. Several techniques are available to achieve both low active and standby power SRAM without using a low supply voltage. When even after power optimization the SRAMs consume a large part of system power, low voltage SRAM further reduces power consumption. Using statistical simulation techniques, robustness for low power SRAM is ensured without over-design.
机译：尽管SRAM面临来自外部DRAM的激烈竞争，但它的低等待时间对数字IC仍然很重要。随着最近对“绿色”产品的关注，数字系统的功耗降低一直是人们关注的焦点，因此低功耗SRAM设计也是如此。对于许多系统而言，正确设计的SRAM对SoC总功耗的贡献很小，这意味着低电压SRAM所需的大量设计工作不会奏效。有几种技术可用于在不使用低电源电压的情况下实现低有效功耗和待机功耗SRAM。即使在功耗优化后，SRAM仍消耗了很大一部分系统功率，低压SRAM仍会进一步降低功耗。使用统计仿真技术，可确保低功耗SRAM的鲁棒性而无需过度设计。

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