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首页> 外文期刊>Journal of Low Power Electronics >New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET
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New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET

机译：使用独立控制的双栅极FinFET的未来工艺，电压和温度感知SRAM的新拓扑方法

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摘要

As the technology is moving towards nanoscaled device dimensions, the Process, Voltage and Temperature (PVT) variations have become dominant parameters of increased SRAM failure probability and loss of manufacturing yield. In this paper, we proposed three Independently controlled double-Gate FinFET (IDG-FinFET) based SRAM topologies for PVT tolerant and high performance SRAM. Back-gate biasing is explored to enhance stability and write performance along-with lower leakage. The built-in feedback mechanism is employed to achieve variation tolerant design during read and standby operations. Inter and intra-die process variations are targeted simultaneously for stability and performance analysis for which six sigma deviations in Static Noise Margin and Read Noise Margins due to intrinsic fluctuations alone is projected to demonstrate the stability of topology (cell) using 5000 points Monte-Carlo simulations. As compared with the conventional IDG-FinFET based 10T SRAM topology, the proposed 10T3 SRAM topology increases static noise (SNM), read noise (RNM) and word line write (WLWM) margins by 1.14, 1.11 and 1.5 times, respectively.
机译：随着技术向纳米级器件尺寸发展，工艺，电压和温度（PVT）的变化已成为增加SRAM故障概率和降低生产良率的主要参数。在本文中，我们针对PVT耐受和高性能SRAM提出了三种基于独立控制的双栅极FinFET（IDG-FinFET）的SRAM拓扑。研究了背栅偏置以提高稳定性和写入性能，同时降低泄漏。内置反馈机制用于在读取和待机操作期间实现耐变化的设计。同时针对晶粒间和晶粒间工艺变化进行稳定性和性能分析，其中仅因固有波动而导致的静态噪声裕度和读取噪声裕度的六个西格玛偏差预计将证明使用5000点蒙特卡洛方法展示拓扑（单元）的稳定性模拟。与传统的基于IDG-FinFET的10T SRAM拓扑相比，建议的10T3 SRAM拓扑将静态噪声（SNM），读取噪声（RNM）和字线写入（WLWM）容限分别提高了1.14、1.11和1.5倍。

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