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首页> 外文期刊>Journal of Low Power Electronics >Power-Aware Automated Pipelining of Combinational Circuits
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Power-Aware Automated Pipelining of Combinational Circuits

机译：组合电路的功率感知自动流水线

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Pipelining of combinational circuits with power, area and clock frequency constraints is a very useful way to increase operational speed of circuits. We solve the pipelining problem as a special case of retiming problem combining the effects of area-timing-power trade-off using gate sizing. For design constraints of area, power and gate sizing range, we give heuristic methods to attain pipelining close to optimal power aware minimum latency pipelined circuit. In this paper we formulate this problem as a Mixed Integer Non Linear Programming (MINLP) problem and we provide two heuristic methods to obtain good solutions. The first method is sensitivity based approach which gives good solution to circuits with large number of gates. The second method uses geometric programming method which is slower on large circuits, but works well for smaller designs. The two algorithms are tested on ISCAS-85 benchmark and circuits generated by our tool and compared for speed and efficiency. We study the varying impact of supply, threshold voltage and logic depth per pipeline stage on pipelining efficiency in terms of latency and total power consumption. We extend this method to show power reduction due to supply and threshold voltage scaling and find effective logic depth by varying logic depth per pipelining stage. Simulation work with 130 nm static CMOS model on benchmark circuits show that the effective logic depth per pipeline stage varies considerably for different supply and threshold voltage of the circuit. We find power efficient pipelined designs to operate best at low threshold voltage. Keeping the design constraints fixed, we obsere from our simulations that pipelined designs at certain threshold and supply voltage gives power savings of 10-85% compared to supply and threshold voltage that yield worse power cost. With design constraints fixed except logic depth and at fixed supply and threshold voltage we observe that pipelined design at effective logic depth has 10-60% savings in power cost compared to pipelined design at logic depth over a range of 4-22 FO4 delay.
机译：具有功率，面积和时钟频率约束的组合电路的流水线化是提高电路工作速度的非常有用的方法。我们将流水线问题作为重新定时问题的特例加以解决，结合了使用门选型的区域定时电源权衡的效果。对于面积，功率和栅极尺寸范围的设计约束，我们提供了启发式方法，以使流水线接近最佳功率感知的最小等待时间流水线电路。在本文中，我们将此问题公式化为混合整数非线性规划（MINLP）问题，并提供了两种启发式方法来获得良好的解决方案。第一种方法是基于灵敏度的方法，它为具有大量门的电路提供了很好的解决方案。第二种方法使用几何编程方法，这种方法在大型电路上速度较慢，但​​在较小的设计中效果很好。两种算法均在ISCAS-85基准测试和我们工具生成的电路上进行了测试，并比较了速度和效率。我们从延迟和总功耗的角度研究了每个流水线阶段的电源，阈值电压和逻辑深度对流水线效率的变化影响。我们扩展此方法以显示由于电源和阈值电压缩放而导致的功耗降低，并通过改变每个流水线阶段的逻辑深度来找到有效的逻辑深度。在基准电路上使用130 nm静态CMOS模型进行的仿真工作表明，对于不同的电源和阈值电压，每个流水线级的有效逻辑深度会有很大变化。我们发现高功率流水线设计可以在低阈值电压下最佳运行。保持设计约束固定不变，我们从仿真中发现，流水线设计在特定阈值和电源电压下可比功耗和阈值电压节省10％至85％的功耗，从而降低了功耗。在除逻辑深度和固定电源电压以及阈值电压以外的固定设计约束条件下，我们观察到在有效逻辑深度的流水线设计比在4-22 FO4延迟范围内的逻辑深度的流水线设计节省了10-60％的功耗。

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