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首页> 外文期刊>Journal of Low Power Electronics >Fault-Tolerance in Field Programmable Gate Array with Dynamic Voltage and Frequency Scaling
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Fault-Tolerance in Field Programmable Gate Array with Dynamic Voltage and Frequency Scaling

机译：具有动态电压和频率缩放功能的现场可编程门阵列中的容错

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The purpose of this paper is to present a methodology for Field Programmable Gate Array based designs, either to reduce power consumption or to boost performance during product lifetime. The methodology includes a performance sensor, focusing long-term parametric variations like Process, power-supply Voltage, Temperature and Aging, and a Single Event Upsets' sensor, focusing intermittent variations like radiation effects and disturbances. The performance sensor predictively detects errors in critical paths, either allowing power-supply voltage to be reduced, or clock frequency to be raised, creating a dynamic voltage and frequency scaling technique to reduce power or to increase circuit performance. Fault-tolerance is enhanced not only by predictively detecting errors in performance sensors, but also by using of traditional fault-tolerance solutions like Triple-Modular Redundancy or Error Correcting Codes. The Single Event Upsets' sensor monitors Single Event Upsets in Block Random Access Memory, which allows a faster evaluation of radiation effects than the configuration memory monitoring, thus increasing error detection and correction. The Hardware Description Language sensor's functionality is defined by the designer, according to the target circult configuration in the Field Programmable Gate Arrays' structure. The adaptive scheme uses an Automatic Voltage and Frequency Controller to modify power-supply voltage and/or clock frequency, while still guaranteeing safe operation. The built-in performance sensors monitor performance deviations in pre identified critical paths during circuit operation. The clock frequency increase is made possible by reducing the pessimistic safety margins defined by standard simulation tools to account for variability. The performance sensors delay margins are programmable, so the most adequate delay margin can be used to guarantee safe operation. Conversely, the same performance can be achieved with lower power-supply voltage. Simulation and experimental results with Virtex 5 and Spartan 6 boards show that significant performance improvements (typically, 30%) can be achieved with this methodology.
机译：本文的目的是提出一种基于现场可编程门阵列的设计方法，以降低功耗或提高产品寿命期间的性能。该方法包括一个性能传感器，可集中处理过程，电源电压，温度和老化等长期参数变化，以及一次事件扰动的传感器，可集中处理辐射效应和干扰等间歇性变化。性能传感器可预测性地检测关键路径中的错误，从而允许降低电源电压或提高时钟频率，从而创建了动态电压和频率缩放技术来降低功耗或提高电路性能。不仅通过预测性地检测性能传感器中的错误，而且通过使用传统的容错解决方案（如三模块冗余或纠错码）来提高容错能力。 Single Event Upsets的传感器监视块随机存取存储器中的Single Event Upset，与配置存储器监视相比，它可以更快地评估辐射效应，从而提高了错误检测和纠正的能力。硬件描述语言传感器的功能由设计人员根据现场可编程门阵列结构中的目标杂散配置定义。自适应方案使用自动电压和频率控制器来修改电源电压和/或时钟频率，同时仍保证安全操作。内置的性能传感器可在电路运行期间监视预先确定的关键路径中的性能偏差。通过减少标准仿真工具定义的悲观安全裕度来考虑可变性，可以提高时钟频率。性能传感器的延迟裕量是可编程的，因此可以使用最适当的延迟裕量来保证安全操作。相反，较低的电源电压可以实现相同的性能。 Virtex 5和Spartan 6电路板的仿真和实验结果表明，采用这种方法可以显着提高性能（通常为30％）。

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