...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>Journal of Micromechanics and Microengineering >High-step-coverage Cu-lateral interconnections over 100 μm thick chips on a polymer substrate - an alternative method to wire bonding
【24h】

High-step-coverage Cu-lateral interconnections over 100 μm thick chips on a polymer substrate - an alternative method to wire bonding

机译：在聚合物基板上覆盖100μm厚芯片的高台阶覆盖率的Cu侧向互连-引线键合的另一种方法

获取原文
获取原文并翻译 | 示例
   

获取外文期刊封面封底 >>

       
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

We propose a novel chip in the polymer board interconnect method for packaging different kinds of chips on a wafer level, where conventional wire bonding may not be possible due to either space or mechanical constraints. High-step-coverage copper (Cu)-lateral interconnects formed over 100 μm thick Si chips by the electroplating method have been investigated for their microstructure and electrical characteristics, using the field emission scanning electron microscope and semiconductor parameter analyzer (Agilent, 4156C). The obtained coverage ratios (i.e. the layer thickness on the chip surface to the sidewall of the chip) for each formed layer, i.e. the tantalum barrier layer, Cu seed layer, SiO_2 dielectric layer and electroplated Cu layer, were 3:1, 3:1, 1.5:1 and 1:1, respectively. The measured mean electrical resistances for 36 μm × 2000 μm and 58 μm × 2000 μm interconnect lines were respectively 31.1 and 24 mΩ, and the difference between measured and calculated resistance values was less than 5%. The good quality of as-fabricated Cu-lateral interconnects was evidenced from the observed low resistance values for isolated interconnects and the linear change in daisy chain resistance with the number of interconnects. More importantly, even at a high operating temperature of 150℃, the resistance value of the Cu-lateral interconnect over the integrated chip was very close to that of the resistance value of interconnect on the plain wafer. The suitability of this technique in integrating various chips heterogeneously was validated from the no observed change in transistor behavior due to this technique. Since this is a CMOS compatible interconnection method between the polymer substrate and chip, it can readily be scaled up to the wafer level.
机译：我们在聚合物板互连方法中提出了一种新颖的芯片，用于在晶圆级上封装不同种类的芯片，由于空间或机械限制，传统的引线键合可能无法实现。使用场发射扫描电子显微镜和半导体参数分析仪（Agilent，4156C），研究了通过电镀方法在100μm厚的Si芯片上形成的高台阶覆盖铜（Cu）侧向互连的微观结构和电特性。对于每个形成的层，即钽阻挡层，Cu籽晶层，SiO_2介电层和电镀Cu层，获得的覆盖率（即芯片表面到芯片侧壁的层厚）分别为3：1、3： 1、1.5：1和1：1。对于36μm×2000μm和58μm×2000μm互连线，测得的平均电阻分别为31.1和24mΩ，测得的电阻值与计算的电阻值之差小于5％。从观察到的隔离互连的低电阻值以及菊花链电阻随互连数量的线性变化，可以证明所制造的Cu侧向互连的质量良好。更重要的是，即使在150℃的高工作温度下，集成芯片上的铜侧互连的电阻值也非常接近普通晶片上互连的电阻值。从没有观察到由于该技术引起的晶体管行为的变化，验证了该技术在异构集成各种芯片中的适用性。由于这是聚合物基板和芯片之间的CMOS兼容互连方法，因此可以很容易地按比例放大到晶圆级。

著录项

相似文献

  • 外文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号