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首页> 外文期刊>WSEAS Transactions on Signal Processing >Comparative Analysis of Two Op-Amp Topologies for a 40MS/s 8-bit Pipelined ADC in 0.18μm CMOS Technology
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Comparative Analysis of Two Op-Amp Topologies for a 40MS/s 8-bit Pipelined ADC in 0.18μm CMOS Technology

机译：在0.18μmCMOS技术中为40ms / s 8位流水线ADC进行两种OP-AMP拓扑的比较分析

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摘要

The performances of two full differential operational amplifiers (Op-Amps) telescopic and folded-cascode are evaluated to satisfy the stringent requirements on the amplifier to be used in a Multiplying Digital-to-Analog Converter (MDAC) stage of a pipelined ADC (Analog-to-Digital Converter). The paper shows the solutions found to reach high gain, wide bandwidth and short settling time without degrading too much the output swing. The Op-Amp specifications are extracted according to the ADC requirements, then the two Op-Amp topologies are designed, tested and their performances are compared. Simulation results show that the Op-Amp folded-cascode topology is more suitable architecture for pipelined ADC than the telescopic one. Moreover, the use of this type of Op-Amp generates an Integral Non-Linearity (INL) error less than that of the telescopic one. The analyses and simulation results are obtained using 0.18 μm AMS (Austria Mikro System) CMOS process parameters with a power supply voltage of 1.8V. The predicted performance is verified by analysis and simulations using Cadence EDA simulator.
机译：评估两个全差分运算放大器（OP-AMPS）伸缩和折叠共级焦点的性能，以满足在流水线ADC的乘法数模型转换器（MDAC）阶段的放大器上的严格要求（模拟 - 数字转换器）。本文显示了发现达到高增益，宽带宽和短稳定时间的解决方案，而不会降低输出摆幅。根据ADC要求提取OP-AMP规范，然后设计了两个OP-AMP拓扑结构，并比较了它们的性能。仿真结果表明，OP-AMP折叠式Cascode拓扑比伸缩式ADC更合适的架构。此外，这种类型的OP-AMP的使用产生的积分非线性（INL）误差小于伸缩式误差。分析和仿真结果是使用0.18μm（奥地利mikro系统）CMOS工艺参数获得的，电源电压为1.8V。使用Cadence EDA Simulator进行分析和模拟验证预测性能。

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