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The large-scale integration of high-performance silicon nanowire field effect transistors

机译:高性能硅纳米线场效应晶体管的大规模集成

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摘要

In this work we present a CMOS-compatible self-aligning process for the large-scale-integration of high-performance nanowire field effect transistors with well-saturated drain currents, steep subthreshold slopes at low drain voltage and a large on/off current ratio (>10(7)). The subthreshold swing is as small as 45 mV/dec, which is substantially beyond the thermodynamic limit (60 mV/dec) of conventional planar MOSFETs. These excellent device characteristics are achieved by using a clean integration process and a device structure that allows effective gate-channel-source coupling to tune the source/drain Schottky barriers at the nanoscale.
机译:在这项工作中,我们提出了一种用于大规模集成高性能纳米线场效应晶体管的CMOS兼容自对准工艺,该晶体管具有良好饱和的漏极电流,低漏极电压下的亚阈值斜率以及大的开/关电流比(> 10(7))。亚阈值摆幅小至45 mV / dec,大大超出了常规平面MOSFET的热力学极限(60 mV / dec)。这些优异的器件特性是通过使用干净的集成工艺和器件结构实现的,该器件结构允许有效的栅极-沟道-源极耦合,从而在纳米级调整源/漏肖特基势垒。

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