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首页> 外文期刊>Nanotechnology >Electrical characterization of Mgh-dielectric-constant/SiO_2 metal-oxide-semiconductor gate stacks by a conductive atomic force microscope
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Electrical characterization of Mgh-dielectric-constant/SiO_2 metal-oxide-semiconductor gate stacks by a conductive atomic force microscope

机译：导电原子力显微镜对Mgh-介电常数/ SiO_2金属氧化物半导体栅叠层的电学表征

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A conductive atomic force microscope (CAFM) has been used to study, at the nanometre scale, the dependence of the electrical behaviour on the post-deposition annealing temperature (7X) and the dielectric reliability of ultrathin high-dielectric-constant/SiO_2 MOS gate stacks. It has been observed that for high enough TA the conduction becomes more inhomogeneous, leading to the formation of leaky spots that could be a problem for the integration of these layers in a standard CMOS microelectronic process. The CAFM has also revealed that the values of some parameters related to the dielectric reliability, such as the area of the breakdown spot (i.e. a region that has lost its insulating properties owing to electrical stress), are of the same order for SiO_2 layers and high-dielectric-constant/SiO_2 stacks. Moreover, different conduction regimes, which cannot be detected by standard electrical characterization techniques, have been observed.
机译：导电原子力显微镜（CAFM）已用于研究纳米级电行为对沉积后退火温度（7X）和超薄高介电常数/ SiO_2 MOS栅极的介电可靠性的依赖性堆栈。已经观察到，对于足够高的TA，传导变得更加不均匀，导致形成泄漏点，这对于在标准CMOS微电子工艺中这些层的集成可能是一个问题。 CAFM还显示，与介电可靠性相关的某些参数的值，例如击穿点的面积（即由于电应力而失去绝缘性能的区域）对于SiO_2层和高介电常数/ SiO_2叠层。此外，已经观察到了不同的传导方式，这些传导方式无法通过标准的电特性技术来检测。

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