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首页> 美国政府科技报告 >Delay-Insensitive Multiply-Accumulate Unit.
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Delay-Insensitive Multiply-Accumulate Unit.

机译：延迟不敏感乘法累加单元。

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Due to advances in integration technology the use of asynchronous circuits has become increasingly interesting. Design methods have emerged with which it is manageable to design efficient and reliable asynchronous circuits. Instead of designing circuits under worst case assumptions as for synchronous circuits, the objective in asynchronous design is to attain the best possible average performance and to utilize this potential performance advantage at the architectural level. We have designed a serial-parallel multiply-accumulate unit that exploits this performance advantage. The unit is designed to be part of a large ring network of units performing vector-matrix multiplications.

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