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Delay Modeling of Bipolar ECL/EFL (Emitter-Coupled Logic/Emitter-Follower-Logic) Circuits

机译：双极ECL / EFL（发射极耦合逻辑/发射极 - 跟随器 - 逻辑）电路的延迟建模

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This report deals with the development of a delay-time model for timing simulation of large circuits consisting of Bipolar ECL(Emitter-Coupled Logic) and EFL (Emitter-Follower-Logic) networks. This model can provide adequate information on the performance of the circuits with a minimum expenditure of computation time. This goal is achieved by the use of proper circuit transient models on which analytical delay expressions can be derived with accurate results. The delay-model developed in this report is general enough to handle complex digital circuits with multiple inputs or/and multiple levels. The important effects of input slew rate are also included in the model. (Author)

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作者
Yang, A. T.;
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年度 1986
页码 p.1-79
总页数 79
原文格式 PDF
正文语种 eng
中图分类工业技术;
关键词
Logic circuits; Bipolar transistors; Electronic switches; Computerized simulation; Mathematical models; Equivalent circuits; Delay circuits; Emitters; Coupling(Interaction); Capacitance; Digital systems; Networks; Bases(Transistors); Charge carriers; Transients;

机译：逻辑电路;双极晶体管;电子开关;计算机模拟;数学模型;等效电路;延迟电路;发射器;耦合（相互作用）;电容;数字系统;网络;基极（晶体管）;电荷载体;瞬态;

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专利

1. Modelling and analysis of bridging faults in emitter-coupled logic (ECL) circuits [J] . Menon S.M., Jayasumana A.P. IEE Proceedings. Part E . 1993,第4期

机译：发射极耦合逻辑（ECL）电路中桥接故障的建模和分析
2. Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits [J] . Fang W. IEEE Journal of Solid-State Circuits . 1990,第2期

机译：ECL和CML电路的准确分析延迟表达式及其在优化高速双极性电路中的应用
3. Predicted propagation delay of Si/SiGe heterojunction bipolar ECL circuits [J] . Shafi Z.A., Ashburn P. IEEE Journal of Solid-State Circuits . 1990,第5期

机译：Si / SiGe异质结双极ECL电路的预计传播延迟
4. The Architecture, Logic, and Circuit Design of a Bipolar, 200 Mbyte/sec, Serializing Data Mover IC, with 32-Bit TTL-Compatible Parallel I/O and Unique 1.8 Gbit/sec 'Cutoff Driver1 Differential PECL Serial I/O [C] . Phil Jeffery, David Ford, Phuc Pham, Proceedings of the 1995 Bipolar/BiCMOS circuits and technology meeting . 1995

机译：具有32位TTL兼容并行I / O和独特的1.8 Gbit / sec'Cutoff Driver1差分PECL串行I / O的双极性，200 Mb / sec，串行化数据移动器IC的架构，逻辑和电路设计
5. Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures. [D] . Tang, Aoxiang. 2015

机译：低功耗FinFET逻辑电路和架构的延迟/功率建模和优化技术。
6. Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model [O] . Omnia S. Fadl, Mohamed F. Abu-Elyazeed, Mohamed B. Abdelhalim, 2016

机译：具有实际门延迟模型的CMOS组合逻辑电路的准确动态功率估算
7. Analytical models for delay and power analysis of zero-V load unipolar thin-film Transistor Logic Circuits [O] . Cui Q, Liu W, Guo X, 2014

机译：零伏负载单极薄膜晶体管逻辑电路的延迟和功率分析的分析模型

Delay Modeling of Bipolar ECL/EFL (Emitter-Coupled Logic/Emitter-Follower-Logic) Circuits

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