Simultaneous switching noise was calculated for a number of CMOS drivers switching together. CMOS receiver noise immunity and the feed through of simultaneous switching noise from a D.C. "ON" driver were studied. The effects of skewing output driver switching on the simultaneous switching noise were explained. The performance trade-offs in using a damping resistor to minimize switching noise were analyzed. A distributed lumped equivalent model has been developed to model signal propagation over noisy reference planes, and thereby to accurately predict the overall noise levels in a system. The impact of package pin distribution on noise on the reference plane was analyzed.
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