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Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits

机译：同时开关噪声对数字CMOS电路静态性能的影响

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This paper analyzes the logic errors in digital circuits due to the presence of Simultaneous Switching Noise (SSN). It is demonstrated that 2 conditions must be fulfilled in order to guarantee the correct logic behaviour of a digital circuits. The first condition called "Minimum Switch Condition' is proved to be fulfilled whatever the amount of SSN in the power and ground lines. The second condition called "Signal Coherence Condition" is proved to be fulfilled within power coherent logic blocks. However the interface between non-coherent logic blocks may originate logic dysfunction. DFT and ATPG recommendations are derived from this analysis.

机译：本文分析了由于同时开关噪声（SSN）的存在而引起的数字电路中的逻辑错误。已经证明必须满足两个条件才能保证数字电路的正确逻辑行为。无论电源线和地线中的SSN数量如何，第一个条件“最小切换条件”都可以满足；第二个条件“信号相干条件”可以在电源相干逻辑块内满足。非相干逻辑块可能会导致逻辑功能障碍，DFT和ATPG建议来自此分析。

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来源
《16th Asian Test Symposium》|2007年|239-244|共6页
会议地点 Beijing(CN);Beijing(CN)
作者
LIN Zhilei;
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作者单位

F. Azais@LIRMM, CNRS/University of Montpellier, 161 rue Ada-34392 Montpellier Cedex 5-France--L. Larguier@LIRMM, CNRS/University of Montpellier, 161 rue Ada-34392 Montpellier Cedex 5-France--M. Renovell@LIRMM, CNRS/University of Montpellier, 161 rue Ada-34392 Montpellier Cedex 5-France--;

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正文语种 eng
中图分类调整、测试;
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专利

1. Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching [J] . Tan-Li Chou, Roy K. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 1996,第10期

机译：考虑信号相关性和同时切换的静态和多米诺CMOS电路的活动估计
2. Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise [J] . Senthinathan R., Prince J.L. IEEE Journal of Solid-State Circuits . 1993,第12期

机译：专用CMOS输出驱动器电路设计技术，可降低同步开关噪声
3. Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits [J] . Shin Y., Heo S., Kim H.-O., IEEE transactions on very large scale integration (VLSI) systems . 2007,第7期

机译：具有地塌陷的电源开关：同时控制纳米级CMOS电路中的亚阈值和栅极泄漏电流
4. Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits [C] . Azais F., Larguier L., Renovell M., Asian Test Symposium . 2007

机译：同时开关噪声对数字CMOS电路静态行为的影响
5. Signal integrity and simultaneous switching noise of CMOS devices and systems. [D] . Senthinathan, Ramesh. 1992

机译：CMOS器件和系统的信号完整性和同时开关噪声。
6. Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors [O] . Shoji Kawahito, Min-Woong Seo 2014

机译：用于超低噪声CMOS图像传感器的基于多采样的信号读取电路的降噪效果
7. Simultaneous switching noise and its impact on CMOS digital systems [O] . Nimmagadda Srinivas 1968- 1992

机译：同时开关噪声及其对CMOS数字系统的影响

Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits

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