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IMPROVED CLADDING LAYER EPITAXY VIA TEMPLATE ENGINEERING FOR HETEROGENEOUS INTEGRATION ON SILICON
IMPROVED CLADDING LAYER EPITAXY VIA TEMPLATE ENGINEERING FOR HETEROGENEOUS INTEGRATION ON SILICON
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机译：通过模板工程改进的包覆层表观外延，用于硅上的异质结合
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摘要
A semiconductor body comprising a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body comprising: a first material comprising a first band gap; And a second material comprising a second band gap different from the first band gap, wherein the plurality of nanowires are separated through the first material such that the first material surrounds each of the plurality of nanowires. Placed on the planes-including-; And a gate stack disposed on the channel region. Forming a plurality of nanowires in separate planes on the substrate, each of the plurality of nanowires comprising a material comprising a first band gap; Individually forming a cladding material around each of the plurality of nanowires, the cladding material comprising a second band gap; Joining the cladding material; And placing a gate stack on the cladding material.
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