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Fractional-N phase locked loop, operation method thereof, and devices having the same

机译:N阶分数阶锁相环,其操作方法以及具有该分数阶锁相环的装置

摘要

A fractional-N phase locked loop is provided. The fractional-N phase locked loop includes a phase adjusting circuit detecting a phase difference between a reference clock signal and a feedback clock signal and outputting a plurality of phase clock signals in response to the detected phase difference, a phase selector selecting and outputting one of the plurality of phase clock signals output from the phase adjusting circuit in response to a phase selection signal, a control circuit generating the phase selection signal by using a sigma-delta modulator operation clock signal, which is generated by dividing the selected phase clock signal by each of N or more different integers (N is an integer more than or equal to 2), and a first divider generating the feedback clock signal by dividing the selected phase clock signal by an integer.
机译:提供了分数N锁相环。分数N锁相环包括:相位调整电路,其检测参考时钟信号与反馈时钟信号之间的相位差并响应于检测到的相位差而输出多个相位时钟信号;相位选择器选择并输出以下之一响应于相位选择信号而从相位调节电路输出的多个相位时钟信号,控制电路通过使用∑-Δ调制器操作时钟信号来生成相位选择信号,该信号是通过将所选择的相位时钟信号除以N个或更多不同整数中的每一个(N是大于或等于2的整数),以及第一除法器,该第一除法器通过将所选择的相位时钟信号除以整数来生成反馈时钟信号。

著录项

  • 公开/公告号US9094023B2

    专利类型

  • 公开/公告日2015-07-28

    原文格式PDF

  • 申请/专利权人 JONG SHIN SHIN;

    申请/专利号US201113228520

  • 发明设计人 JONG SHIN SHIN;

    申请日2011-09-09

  • 分类号H03D3/24;H03L7/081;H03L7/18;H03L7/099;H03L7/197;H04L27/00;

  • 国家 US

  • 入库时间 2022-08-21 15:18:42

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