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Interface circuit of various clock period between a fast slope signal and a very slow slope, voltage controlled delay cell
Interface circuit of various clock period between a fast slope signal and a very slow slope, voltage controlled delay cell
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机译：快速斜率信号和非常慢斜率之间的各种时钟周期的接口电路，压控延迟单元
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摘要
A particular wide band interface circuit provides an interface between a very fast slope clock signal input and a very slow slope voltage controlled delay cell of a delay lock loop. The invention generates the internal clock signal to track the slope of each delay stage, whether it is a higher frequency for which the slope of the delay stage is faster or a lower frequency for which the slope of the delay stage is slower. The integrated circuit includes a voltage bias portion, an analog clock input portion, circuit devices for interfacing with clock frequency inputs over all the available frequency range, and an output portion for producing clock signals. The invention applies to the multiple delay stages of a delay lock loop.
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