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首页> 外文会议>42nd international symposium on microelectronics (IMAPS 2009) >Underfill Selection for Flip Chip BGA Warpage Control
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Underfill Selection for Flip Chip BGA Warpage Control

机译：倒装芯片BGA翘曲控制的底部填充选择

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摘要

Flip chip packages are becoming more popularrndue to many factors such as electrical performance,rnfunctionality and high I/O interconnections. To fulfillrnsuch needs in different applications, chip sizes arerngradually becoming larger. Due to the large die sizesrnwith high pin count, small bump pitch and low-Krninter-metal-dielectric material, reliability concernsrnare arising at the interfaces of die, solder bumps andrnsubstrate. Of concern are package warpage issues,rnbump cracks, underfill void/delamination/cracks andrndie cracks, etc. The reliability issues can be solvedrnby selecting more appropriate underfill materials tornrelief mechanical stress from CTE mismatch. Manyrncommercial brands of underfill materials arernavailable in the market and the underfill propertiesrnsuch as Tg, modulus, CTE, viscosity, flowrncharacteristics, and adhesion need to be characterizedrnbefore implementation. In this project, the underfillrnproperties are studied and discussed and stressrnmodeling for large dice in large packages isrnperformed. Package data such as warpage, bumprncrack and delamination are measured for verification.rnThe optimum underfill material for large die flip chiprnpackages has been implemented in mass production.rn[1][2].
机译：由于许多因素，例如电气性能，功能性和高I / O互连，倒装芯片封装正变得越来越流行。为了满足不同应用中的这种需求，芯片尺寸逐渐变大。由于管芯尺寸大，引脚数高，凸块间距小和金属间介电常数低，在管芯，焊料凸块和基板的界面处会出现可靠性问题。值得关注的是封装翘曲问题，隆起裂纹，底部填充空隙/分层/裂纹和模具破裂等。可靠性问题可以通过选择更合适的底部填充材料来解决CTE不匹配引起的机械应力来解决。市场上可买到许多商业品牌的底部填充材料，并且在实施之前需要对底部填充性能（例如Tg，模量，CTE，粘度，流动特性和附着力）进行表征。在这个项目中，研究和讨论了底部填充性能，并对大型包装中的大骰子进行了应力建模。测量了诸如翘曲，凸点裂纹和分层等封装数据以进行验证。rn大批量倒装芯片封装的最佳底部填充材料已实现批量生产。rn[1] [2]。

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  • 来源
  • 会议地点 San Jose CA(US);San Jose CA(US)
  • 作者

    Antony Lin; CY Li; Meng-Kai Shih; Yi-Shao Lai; Bernd Appelt; Andy Tseng;

  • 作者单位

    Advanced Semiconductor Engineering, Inc.rn26 Chin 3rd Rd., Nantze Export Processing Zone, Nantze, Kaohsiung, Taiwan, R.O.C. antony_lin@aseglobal.com +1-408-986-6502;

    rnAdvanced Semiconductor Engineering, Inc.rn26 Chin 3rd Rd., Nantze Export Processing Zone, Nantze, Kaohsiung, Taiwan, R.O.C. cy_li@aseglobal.com +1-408-986-6502;

    rnAdvanced Semiconductor Engineering, Inc.rn26 Chin 3rd Rd., Nantze Export Processing Zone, Nantze, Kaohsiung, Taiwan, R.O.C. ericmk_shih@aseglobal.com +1-408-986-6502;

    rnAdvanced Semiconductor Engineering, Inc.rn26 Chin 3rd Rd., Nantze Export Processing Zone, Nantze, Kaohsiung, Taiwan, R.O.C. yishao_lai@aseglobal.com +1-408-986-6502;

    rnASE (US) INC. 3590 Peterson Way, Santa Clara, California, 95054, USA bernd.appelt@aseus.com +1-408-986-6502;

    rnASE (US) INC. 3590 Peterson Way, Santa Clara, California, 95054, USA andy.tseng@aseus.com +1-408-986-6502;

  • 会议组织
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 微电子学、集成电路（IC）;
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