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首页> 外文会议>Advances in Electronic Packaging 2005 pt.A >WAFER-LEVEL PACKAGING TECHNOLOGY WITH THROUGH-HOLE INTERCONNECTIONS IN SILICON SUBSTRATE
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WAFER-LEVEL PACKAGING TECHNOLOGY WITH THROUGH-HOLE INTERCONNECTIONS IN SILICON SUBSTRATE

机译：硅基体中通过孔互连的晶圆级包装技术

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摘要

An advanced packaging technology with through-hole interconnections, which enables miniaturization and high-density packaging of electronic devices including MEMS devices and optical devices, has been developed. In this work, through-hole interconnections were applied to an image sensor packaging. Through-holes, 80μm in diameter and 200μm in depth, were formed from backside of the device wafer by Deep Reactive Ion Etching (DRIE). After an insulation layer was formed inside the holes, conductive material such as copper (Cu) or Gold-Tin (Au-Sn) alloy solder was filled into the holes by electroplating method or Molten Metal Suction Method (MMSM). This technology enables wafer-level packaging of the image sensor device. Some electrical characteristics and reliability performances including electric resistance, breakdown voltage, high-temperature storage test, heat cycle test, temperature-humidity test were examined. In this paper, fabrication processes, structural and electrical characteristics and reliability of the package will be reported.
机译：已经开发了具有通孔互连的先进封装技术，该技术使得能够对包括MEMS器件和光学器件的电子器件进行小型化和高密度封装。在这项工作中，通孔互连应用于图像传感器封装。通过深度反应离子刻蚀（DRIE）在器件晶圆的背面形成了直径为80μm，深度为200μm的通孔。在孔内形成绝缘层后，通过电镀法或熔融金属抽吸法（MMSM）将诸如铜（Cu）或金锡（Au-Sn）合金焊料之类的导电材料填充到孔中。这项技术可以实现图像传感器设备的晶圆级封装。检查了一些电特性和可靠性性能，包括电阻，击穿电压，高温存储测试，热循环测试，温湿度测试。在本文中，将报告封装的制造工艺，结构和电气特性以及可靠性。

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