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Electrically Driven Optical Proximity Correction

机译:电驱动光学邻近校正

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摘要

Existing optical proximity correction tools aim at minimizing edge placement errors (EPE) due to the optical and resist process by moving mask edges. However, in low-kl lithography, especially at 45nm and beyond, printing perfect polygons is practically impossible to achieve in addition to incurring prohibitively high mask complexity and cost. Given the impossibility of perfect printing, we argue that aiming to reduce the error of electrical discrepancy between the ideal and the printed contours is a more reasonable strategy. In fact, we show that contours with non-minimal EPE may result in closer match to the desired electrical performance. Towards achieving this objective, we developed a new electrically driven OPC (ED-OPC) algorithm. The tool combines lithography simulation with an accurate contour-based model of shape electrical behavior to predict the on/off current through a transistor gate. The algorithm then guides edge movements to minimize the error in current, rather than in edge placement, between current values for printed and target shapes. The results on industrial 45nm SOI layouts using high-NA immersion lithography models show up to a 5% improvement in accuracy of timing over conventional OPC, while at the same time showing up to 50% reduction in mask complexity for gate regions. The results confirm that better timing accuracy can be achieved despite larger edge placement error.
机译:现有的光学邻近校正工具旨在通过移动掩模边缘来减小由于光学和抗蚀剂处理而引起的边缘放置误差(EPE)。但是,在低kl光刻技术中,尤其是在45nm及以后的光刻技术中,除了导致极高的掩模复杂性和成本外,几乎不可能实现印刷完美的多边形。考虑到不可能进行完美印刷,我们认为减少理想轮廓和印刷轮廓之间电气差异的误差是一种更合理的策略。实际上,我们显示出具有非最小EPE的轮廓可能导致与所需电气性能的更紧密匹配。为了实现这一目标,我们开发了一种新的电动OPC(ED-OPC)算法。该工具将光刻仿真与形状电气行为的基于轮廓的精确轮廓模型相结合,以预测通过晶体管栅极的开/关电流。然后,该算法将引导边缘移动,以最大程度减少打印形状和目标形状的当前值之间的电流误差,而不是边缘位置误差。使用高NA浸没式光刻模型的工业45nm SOI布局的结果显示,与传统的OPC相比,时序精度提高了5%,同时,栅极区域的掩模复杂度降低了50%。结果证实,尽管存在较大的边缘放置误差,仍可以实现更好的定时精度。

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