COMPATIBILITY OF POLYSILICON WITH HFO_2-BASED GATE DIELECTRICS FOR CMOS APPLICATIONS

机译：多晶硅与基于HFO_2的栅极电介质在CMOS应用中的相容性

获取原文

获取原文并翻译 | 示例

页面导航

摘要
著录项
相似文献
相关主题

摘要

The compatibility of HfO_2 gate dielectric films using polysilicon deposited under varying conditions as gate electrode has been systematically studied. Gate leakage current of capacitors was monitored as a metric for compatibility. Measurements after activation anneals show that for HfO_2 films, low temperature amorphous depositions show low leakage while with crystalline polySi depositions shorted capacitors resulted. For the HrO_2 films covered by a capping layer, the crystalline poly depositions show lower leakage than amorphous depositions. The high leakage with crystalline polysilicon electrodes is speculated as being due to the presence of weak spots or defects in the film which in the presence of a reducing ambient during polySi deposition become high-leakage conduction paths. The presence of Si within the HfO_2 film detected by TOF-SIMS supports this hypothesis.

机译：对在不同条件下沉积的多晶硅作为栅电极的HfO_2栅介质膜的相容性进行了系统的研究。监视电容器的栅极泄漏电流作为兼容性的度量。活化退火后的测量结果表明，对于HfO_2薄膜，低温非晶沉积显示出低泄漏，而结晶多晶硅沉积则导致电容器短路。对于被覆盖层覆盖的HrO_2膜，结晶多晶沉积显示出比无定形沉积更低的泄漏。据推测，结晶性多晶硅电极的高泄漏是由于薄膜中存在弱点或缺陷所致，在多晶硅沉积过程中存在还原性环境时，薄膜中会出现弱点或缺陷，从而成为高泄漏的导电路径。通过TOF-SIMS检测到的HfO_2膜中Si的存在支持了这一假设。

著录项

来源
《Electrochemical Society Meeting and International Symposium on ULSI Process Integration III; 20030428-20030502; Paris; FR》|2003年|P.391-396|共6页
会议地点 Paris(FR);Paris(FR)
作者
V.S. Kaushik; S.DeGendt; M.Caymax; E.Young; E.Rohr; S.V.Elshocht; A.Delabie; M. Claes; X.Shi; J.Chen; R.Carter; T.Conard; W.Vandervorst; M.Schaekers; M.Heyns;
展开▼
作者单位

International Sematech, 2706 Montopolis Drive, Austin Texas 78741;

展开▼
会议组织
原文格式 PDF
正文语种 eng
中图分类大规模集成电路、超大规模集成电路;
关键词

相似文献

外文文献
中文文献
专利

1. Compatibility of Hf_xTa_yN metal gate electrode with HfO_xN_y gate dielectric for advanced CMOS technology [J] . Kuei-Shu Chang-Liao, Hsin-Chun Chang, B.S. Sahu, Microelectronic Engineering . 2006,第11a12期

机译：Hf_xTa_yN金属栅电极与HfO_xN_y栅极电介质的兼容性，可用于先进的CMOS技术
2. Sub-1/4-/spl mu/m dual-gate CMOS technology using in-situ doped polysilicon for nMOS and pMOS gates [J] . Okazaki Y., Kobayashi T. IEEE Transactions on Electron Devices . 1995,第9期

机译：低于1/4 / splμm/ m的双栅极CMOS技术，使用用于nMOS和pMOS栅极的原位掺杂多晶硅
3. Positive bias temperature instability of HfO_2-based gate stacks at reduced thermal budget for future CMOS technologies [J] . D. Claes, J. Franco, N. Collaert, Journal of Applied Physics . 2020,第10期

机译：基于HFO_2的栅极堆栈的正偏置温度不稳定性，减少了CMOS技术的热预算
4. Compatibility of PolySilicon with HfO_2-based Gate Dielectrics for CMOS Applications [C] . V.S.Kaushik, S.DeGendt, M.Caymax, The Meeting of the Electrochemical Society . 2003

机译：多晶硅与基于HFO_2的栅极电介质的兼容性CMOS应用
5. High-k gate dielectrics for silicon CMOS applications. [D] . Luo, Zhijiong. 2003

机译：用于硅CMOS应用的高k栅极电介质。
6. Design of Higher-k and More Stable Rare Earth Oxides as Gate Dielectrics for Advanced CMOS Devices [O] . Yi Zhao 2012

机译：高k和更稳定的稀土氧化物作为先进CMOS器件的栅极电介质的设计
7. Electrical properties of MOCVD HfO2 dielectric layers with polysilicon gate electrodes for CMOS applications [O] . Date L, Rittersma ZM, Massoubre David, 2003

机译：用于CMOS应用的具有多晶硅栅电极的MOCVD HfO2介电层的电性能

COMPATIBILITY OF POLYSILICON WITH HFO_2-BASED GATE DIELECTRICS FOR CMOS APPLICATIONS

摘要

著录项

相似文献

相关主题

期刊订阅