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首页> 外文会议>Electron-Beam, X-Ray, and Ion-Beam Submicrometer Lithographies for Manufacturing IV >Supporting early development of advanced high-performance logic with synchrotron orbital radiation lithography: a feasibility evaluation
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Supporting early development of advanced high-performance logic with synchrotron orbital radiation lithography: a feasibility evaluation

机译：用同步加速器轨道辐射光刻支持早期高性能逻辑的早期开发：可行性评估

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Abstract: The synchrotron x ray lithography (XRL) projectdescribed was conducted as a learning and feasibilityvehicle for gate level lithography in support of IBM'smost advanced CMOS logic programs. An electricallyprobable multilevel lithography test site was developedand characterized to exercise critical design, maskmanufacture, alignment, exposure, and metrology issuesin the 150 - 350 nm linewidth range. A fully cappedsilicided polysilicon gate stack was chosen for theelectrical measurements in order to develop anddemonstrate the XRL and related reactive ion etchprocess on a realistic, product-like substrate. Thispaper addresses test site design issues, elaborates onthe mask manufacturing process, and presents SEM andelectrical data from wafers processed at IBM's AdvancedSemiconductor Technology Center. The data presenteddemonstrate the feasibility of supporting early devicedevelopment and process integration with XRL andhighlight the need for high resolution, defect free,proximity corrected masks to fully exploit thecapabilities of x ray lithography. !3
机译：摘要：所描述的同步加速器X射线光刻（XRL）项目是作为门级光刻的学习和可行性工具而进行的，以支持IBM最先进的CMOS逻辑程序。开发了一个电学上可能的多层光刻测试站点，并对其进行了表征，以执行150-350 nm线宽范围内的关键设计，掩模制造，对准，曝光和计量问题。选择完全覆盖的硅化多晶硅栅极叠层进行电学测量，以便在现实的类似产品的基板上开发和演示XRL和相关的反应性离子蚀刻工艺。本文解决了测试现场的设计问题，详细介绍了掩模的制造工艺，并介绍了在IBM AdvancedSemiconductor技术中心处理过的晶圆的SEM和电学数据。所提供的数据证明了支持早期设备开发和与XRL集成的可行性，并强调了对高分辨率，无缺陷，接近校正的掩模以充分利用X射线光刻能力的需求。 ！3

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