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首页> 外文会议>IMAPS 2008 - 41st international symposium on microelectronics: bringing together the entire microelectronics supply chain >Thermal Simulations for 4-Layer Stacked IC Packages
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Thermal Simulations for 4-Layer Stacked IC Packages

机译：四层堆叠IC封装的热仿真

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摘要

Since the shortened wiring length between devices and chips in stacked IC package can reduce the signal delayed effects and improve many electrical characteristics, the topics of stacked IC package are now being studied extensively. Although the electrical benefits are greatly increasing in stacked IC packages, their corresponding thermo-mechanical problems are raising as well, including the problems of heat dissipation, induced stresses, interfacial delamination, via cracking and so on. These problems always cause failures or fatigues in stacked IC packages and become critical reliability issues. In order to obtain thermal distributions in stacked IC packages, the 4-layer stacked IC package (chip on chip) with TSV (through silicon vias) structure has been constructed as our test vehicle in this paper. Not only the temperature distributions but also the junction temperature and thermal resistances in 4-layer stacked IC package have been obtained. In addition, the hot spot effects induced non-uniform temperature distributions in the same structure have also been illustrated. These results will be useful design guidelines to engineers when optimum thermal solutions in 4-layer stacked IC package are demanded.
机译：由于缩短堆叠式IC封装中的器件与芯片之间的布线长度可以减小信号延迟效应并改善许多电气特性，因此，目前正在广泛研究堆叠式IC封装的主题。尽管堆叠式IC封装的电气效益大大提高，但它们相应的热机械问题也在不断增加，包括散热，感应应力，界面分层，开裂等问题。这些问题总是会引起堆叠式IC封装的故障或疲劳，并成为至关重要的可靠性问题。为了获得堆叠式IC封装中的热分布，本文构建了具有TSV（通过硅过孔）结构的4层堆叠式IC封装（单芯片）。不仅获得了4层堆叠IC封装中的温度分布，而且还获得了结温和热阻。另外，还示出了热点效应引起的相同结构中的不均匀温度分布。当需要4层堆叠IC封装的最佳散热解决方案时，这些结果将对工程师有用的设计指南。

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