Novel adaptive probing for wafer level chip scale package

机译：晶圆级芯片规模封装的新型自适应探测

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摘要

To be “More than Moore's law”, Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is more cost-effective than other 3D-integrated-circuit (3DIC) technologies for consumer mobile, wearable, and “Internet-of-Things” (IoT) markets. To further improve the test quality, yield, and cost of InFO WLCSP by probing copper-pillars without solder-caps, adaptive probing is developed to improve traditional fixed probing recipes. Therefore, variations of copper-pillars, wafer warping, and un-coplanarity of high-pin-count probes can be tolerated. According to the characterizations and experimental results, the analyses, strategies, algorithm, and test programs can improve yield, test time, and probe-card lifetime dramatically. The proposed adaptive probing methods can handle not only the worst varied probing case on copper-pillars but also other critical probing cases.

机译：为达到“超越摩尔定律”的目的，集成扇出晶圆级芯片级封装（InFO WLCSP）比其他3D集成电路（3DIC）技术更具成本效益，可用于消费者移动设备，可穿戴设备和“互联网-物联网”（IoT）市场。为了通过探测不带焊帽的铜柱来进一步提高InFO WLCSP的测试质量，成品率和成本，开发了自适应探测以改进传统的固定探测配方。因此，可以容忍铜柱的变化，晶圆翘曲以及高引脚数探针的不共面性。根据特性和实验结果，分析，策略，算法和测试程序可以显着提高良率，测试时间和探针卡寿命。提出的自适应探测方法不仅可以处理铜柱上最差的探测情况，还可以处理其他关键探测情况。

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来源
《Joint 2015 e-Manufacturing amp; Design Collaboration Symposium 2015 and 2015 International Symposium on Semiconductor Manufacturing》|2015年|1-5|共5页
会议地点 Taipei(CT)
作者
Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang;
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作者单位

Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan;

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会议组织
原文格式 PDF
正文语种 eng
中图分类
关键词
Internet of Things; chip scale packaging; three-dimensional integrated circuits; wafer level packaging; 3D IC technologies; 3D integrated circuit; InFO WLCSP; Internet-of-Things; IoT; More than Moores law; adaptive probing methods; copper-pillars; fixed probing recipes; integrated fan-out wafer-level chip-scale packaging; solder-caps; wafer level chip scale package; wafer warping; Algorithm design and analysis; Copper; Joints; Market research; Micromechanical devices; Mobile communication; Probes; Adaptive Test; Copper;

机译：物联网;芯片级封装;三维集成电路;晶圆级封装; 3D IC技术; 3D集成电路; InFO WLCSP;物联网; IoT;摩尔定律以上;自适应探测方法;铜柱;固定探测配方;集成的扇出晶圆级芯片级封装;焊锡帽;晶圆级芯片级封装;晶圆翘曲;算法设计和分析;铜;接头;市场研究;微机械设备;移动通信;探针;自适应测试;铜;

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2. Thin-Film-Flip-Chip LEDs Grown on Si Substrate Using Wafer-Level Chip-Scale Package [J] . Keon Hwa Lee, Mojtaba Asadirad, Shahab Shervin, IEEE Photonics Technology Letters . 2016,第18期

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3. Visible Light-Emitting Diodes With Thin-Film-Flip- Chip-Based Wafer-Level Chip-Scale Package Technology Using Anisotropic Conductive Film Bonding [J] . Lee Keon Hwa, Kim Seung Hwan, Lim Woo-Sik, Electron Device Letters, IEEE . 2015,第7期

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4. Novel adaptive probing for wafer level chip scale package [C] . Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Joint 2015 e-Manufacturing Design Collaboration Symposium 2015 . 2015

机译：晶圆级芯片尺度包装的新型自适应探测
5. Experimental and Simulation Board Level Reliability Assessment of Wafer Level Chip Scale Packages (WCSPs) Under Thermal Cycling [D] . Khan, Hassaan Ahmad 2015

机译：热循环下晶圆级芯片级封装（WCSP）的实验和仿真板级可靠性评估
6. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems [O] . Kenji Okabe, Horagodage Prabhath Jeewan, Shota Yamagiwa, 2015

机译：用于无线供电的神经接口系统的薄膜柔性天线和硅CMOS整流器芯片的协同设计方法和晶圆级封装技术
7. Folded-patch chip-size antennas for wireless microsystems using wafer-level chip-scale packaging [O] . Mendes P. M., Polyakov A., Bartek M., 2003

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Novel adaptive probing for wafer level chip scale package

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