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首页> 外文会议>International VLSI multilevel interconnection conference;VMIC >'FACE TO FACE WAFER BONDING FOR 3D CHIP STACK FABRICATION TO SHORTEN WIRE LENGTHS'
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'FACE TO FACE WAFER BONDING FOR 3D CHIP STACK FABRICATION TO SHORTEN WIRE LENGTHS'

机译：“面对面晶圆键合的3D芯片堆叠制造，缩短了线长”

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Wire parasitics are now a commonly acknowledged limitation on integrated circuit performance. Many valuable materials studies strive to implement interconnections in these circuits with low K dielectric constant insulators and low resistivity metals. Even with these innovations though, several studies show that these innovations will simply push out the wiring "brick wall" a few years further into the future. Strategies are needed to continue to move forward once these basic materials innovations have run their course. Architecture is one area for innovation, but optimum layout of a chip or data path to minimize wiring lengths is a challenge that has been studied for many years, and the prospect for a major breakthrough in this area is slight. Some truly innovative changes will be needed. This paper examines one possibility for implementing 3D chips as a strategy for wire length minimization. This technique is called "Face to Face" wafer lamination, a process that is not terribly dissimilar from wafer bonding in SOI. However in this case the two wafers have circuitry on them already with some wiring layers. The two wafer faces are oxide deposited and planarized by CMP. Then the two planarized surfaces are coated with one of several polymer layers, aligned and bonded using a new aligner specially developed for this project. After bonding, the wafer stack is encapsulated in parylene and the back of the top wafer is re-exposed. The back of the top wafer is then dissolved. This is done using a liquid etch to an oxide stop layer. This removes nearly all the silicon from the top wafer leaving only the silicon device layers and multilayer interconnections left behind still glued to the bottom wafer. Deep vias are then etched from the backside of the top thinned wafer layer through to a metal stopping layer on the bottom wafer. These deep vias are then CVD lined and Cu Filled in a two step process which leaves the via still available at the top for further integration or I/O connection. After repeating these steps for all the layers in the stack (up to 4 steps are considered feasible), the wafer stack is then diced. The paper discusses choices of glue layers, examines the quality of seams in between the two layers, thermal stability for this layer, etching and via filling strategies.
机译：现在，导线寄生效应是集成电路性能普遍公认的局限性。许多有价值的材料研究努力在这些电路中使用低K介电常数绝缘体和低电阻率金属实现互连。尽管有了这些创新，但多项研究表明，这些创新将在未来几年简单地将布线“砖墙”推开。一旦这些基本材料创新成功，就需要采取策略继续前进。架构是创新的领域，但是优化芯片或数据路径以最小化布线长度的挑战是已经研究了很多年的挑战，并且在这一领域取得重大突破的前景很小。需要一些真正的创新性改变。本文研究了一种实现3D芯片作为最小化线长策略的可能性。这项技术称为“面对面”晶圆层压，该工艺与SOI中的晶圆键合并没有很大不同。然而，在这种情况下，两个晶片上已经具有一些布线层的电路。通过CMP沉积两个晶片表面并进行平面化。然后，在两个平面化的表面上涂覆几个聚合物层之一，并使用专门为此项目开发的新型对准器对准并粘结。粘接后，将晶片叠层封装在聚对二甲苯中，并重新暴露顶部晶片的背面。然后将顶部晶片的背面溶解。这是通过对氧化物停止层进行液体蚀刻来完成的。这从顶部晶片去除了几乎所有的硅，仅留下留下的硅器件层和多层互连仍然粘合到底部晶片。然后从顶部变薄的晶片层的背面蚀刻深通孔，直到底部晶片上的金属阻挡层。然后，对这些深孔进行CVD衬里，并在两步过程中填充Cu，使顶部的孔仍可用于进一步集成或I / O连接。在对堆叠中的所有层重复这些步骤（认为最多4个步骤是可行的）之后，将晶圆堆叠切成小块。本文讨论了胶层的选择，检查了两层之间的接缝质量，该层的热稳定性，蚀刻和通孔填充策略。

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