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首页> 外文会议>IEEE Electronic Components and Technology Conference >Full integration of a 3D demonstrator with TSV first interposer, ultra thin die stacking and wafer level packaging
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Full integration of a 3D demonstrator with TSV first interposer, ultra thin die stacking and wafer level packaging

机译：3D演示器与TSV第一中介层，超薄裸片堆叠和晶圆级封装的完全集成

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This work aims at answering to the 3D mega trend of silicon based platform and 3D wafer level packaging (3D-WLSiP). We focus on the development of architectures compliant with high volume markets for applications like mobile telecommunication. In this market, the silicon material will remain the key platform for 3D integration and has to offer the vertical interconnection as well as ultra-thin packages to fit into very slim electronic devices. We have designed both a mechanical demonstrator with daisy chains and a fully functional product based on a silicon interposer, focusing on forward and backward compatibility between Front-End and 3D packaging and the development of a complete set of advanced technological modules: — Thru-silicon-via interconnections (TSV) with copper via-mid technologies. — Ultra-thin (20 and 35 μm) chips fabrication using dicing before grinding (DBG) with 45° beveled edge and plasma stress release technology. — Thin chips stack on the TSV interposer before processing the back side (stacking first) with two different approaches. The first one is a flip chip integration based on Cu/SAC μ-bumps while the second is the Back-to-Face (B2F) way based on high topology RDL after permanent bonding of the chips face up on the interposer. Chip bonding is done with several materials either on die side with die attach film (DAF) or on interposer side using wafer level spin coated polymers. — Thin wafer handling using advanced temporary bonding process to handle the thin silicon interposer wafers during the integration based on BSI product from Brewer Science and ZoneBOND™ technology. Moreover different strategies of handling have been investigated involving high topology temporary bonding as well as carrier flip-flop approaches. — Thin wafer level packaging (TWLP) has been implemented sequentially on front side and back side of the thin resulting in a fully 3D-WLSiP module. Thermo-me- hanical FEM simulation and first reliability assessment using mechanical demonstrator have been carried out and support the good mechanical behaviour of the integration. Electrical tests have been also completed that allows comparing the performances of F2F and B2F interconnection schemes in terms of resistances and yield at front side level but also at back side level after TSV exposure, RDL and bumps. Successful results of development loops have led to start processing a full functional product benefiting of the best process flow.
机译：这项工作旨在应对基于硅平台和3D晶圆级封装（3D-WLSiP）的3D巨型趋势。我们专注于为移动电信等应用开发符合大批量市场的架构。在这个市场中，硅材料将仍然是3D集成的关键平台，并且必须提供垂直互连以及超薄封装，以适合非常纤薄的电子设备。我们既设计了带有菊花链的机械演示器，又设计了基于硅中介层的功能齐全的产品，着重于前端与3D封装之间的向前和向后兼容性以及一整套先进技术模块的开发：—直通硅通孔与铜通孔中间技术的互连。 —使用具有45°斜边和等离子应力释放技术的磨前切割（DBG）来制造超薄（20和35μm）芯片。 —在用两种不同的方法处理背面（先堆叠）之前，将薄芯片堆叠在TSV插入器上。第一个是基于Cu / SACμ凸点的倒装芯片集成，第二个是在芯片永久性地置于中介层上之后，基于高拓扑RDL的Back-to-Face（B2F）方式。芯片键合是通过几种材料完成的，要么是在带有芯片连接膜（DAF）的芯片一侧，要么是使用晶圆级旋涂聚合物的中介层一侧的材料。 —基于先进的临时键合工艺的薄晶圆处理，在集成过程中基于Brewer Science的BSI产品和ZoneBOND™技术处理薄的硅中介层晶圆。此外，已经研究了包括高拓扑结构临时绑定以及载波触发器方法在内的不同处理策略。 —薄晶圆级封装（TWLP）已在薄晶圆的正面和背面依次实现，从而形成了完整的3D-WLSiP模块。使用机械演示器进行了热力学FEM仿真和首次可靠性评估，并支持了集成的良好机械性能。电气测试也已经完成，可以比较F2F和B2F互连方案的性能，包括在TSV暴露，RDL和凸点之后的正面和背面电阻和成品率。开发循环的成功结果使人们开始受益于最佳工艺流程来处理功能齐全的产品。

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