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Sensitivity analysis for SoC performance benchmark against interconnect parasitic resistance and capacitance beyond 10-nm FinFET technology

机译：互连寄生电阻和电容超越10nm FinFET技术的SoC性能基准的敏感性分析

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This paper discusses the performance impact of interconnect parasitic resistance and capacitance for SoC (System on Chip) design beyond 10-nm FinFET technology. As technology scaling advances, the impact of BEOL (Back End of Line) is recognized as one influencer on operating performance. Using typical logic standard cells, sensitivity analysis by DOE (Design of Experiments) shows that the parasitic resistance on wire loads makes a large impact on the cell propagation delay especially with strong cell drivability. Multiple benchmarks show the same tendency that operating performance is degraded by parasitic resistance when strong drivability cells are engaged.

机译：本文讨论了互连寄生电阻和SoC（芯片）设计电容的性能影响超出了10nm FinFET技术。随着技术缩放的进步，BEOL（线路后端）的影响被认为是一个对操作性能的影响因素。使用典型的逻辑标准单元，DOE的灵敏度分析（实验设计）表明，线材负荷对电池传播延迟的寄生电阻尤其是具有强大的细胞驱动性。多个基准测试表明，当强化性电池接合时，通过寄生电阻降低运行性能的趋势。

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《IEEE International System-on-Chip Conference》|2016年|1 v.|共4页
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作者
Motoi Ichihashi; Jia Zeng; Cole Zemke; Irene Lin; Greg Northrop; Ning Jin; Jongwook Kye;
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正文语种
中图分类通信;
关键词
Propagation delay; Benchmark testing; Resistance; Sensitivity analysis; Capacitance; High definition video; Power demand;

机译：传播延迟;基准测试;电阻;敏感性分析;电容;高清视频;电力需求;

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1. Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits [J] . Strangio S., Palestri P., Lanuzza M., Solid-State Electronics . 2017,第FEBa期

机译：考虑基本算术电路的III-V TFET技术平台针对10-nm CMOS FinFET技术节点的基准测试
2. Parasitic Capacitance and Resistance Model Development and Optimization of Raised Source/Drain SOI FinFET Structure for Analog Circuit Applications [J] . Jain Neeraj, Raj Balwinder Journal of Nanoelectronics and Optoelectronics . 2018,第4期

机译：寄生电容与电阻模型开发和升降源/漏极SOI FinFET结构的优化，用于模拟电路应用
3. Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells [J] . Huang Bo-Rong, Meng Fan-Hsuan, King Ya-Chin, Japanese journal of applied physics . 2017,第4S期

机译：研究纳米级FinFET中的寄生电阻和电容效应及其对静态随机存取存储单元的影响
4. Sensitivity analysis for SoC performance benchmark against interconnect parasitic resistance and capacitance beyond 10-nm FinFET technology [C] . Motoi Ichihashi, Jia Zeng, Cole Zemke, IEEE International System-on-Chip Conference . 2016

机译：针对SoC性能基准进行灵敏度分析，以应对超过10nm FinFET技术的互连寄生电阻和电容
5. A parasitic capacitance extraction method for VLSI interconnect modeling [D] . Dengi, Enis Aykut 1997

机译：用于VLSI互连建模的寄生电容提取方法
6. Coexistence of high performance resistance and capacitance memory based on multilayered metal-oxide structures [O] . Z. B. Yan, J. -M. Liu -1

机译：基于多层金属氧化物结构的高性能电阻和电容存储器的共存
7. Benchmarks for Interconnect Parasitic Resistance and Capacitance [O] . Nagaraj Ns, Tom Bonifield, Abha Singh, 2014

机译：互连寄生电阻和电容的基准

Sensitivity analysis for SoC performance benchmark against interconnect parasitic resistance and capacitance beyond 10-nm FinFET technology

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