This paper describes the design of a decimation filter for use with a 4/sup th/ order band-pass /spl Sigma//spl Delta/ modulator adapted for multi-standards wireless transceivers. The simulations undertaken demonstrated that GSM and DECT standards specifications are met by a filtering cascade structure composed of 5/sup th/ order comb filter, 2 half-band filter stages and a droop-correction filter. A fixed-point architectural design was defined and low-power FPGA implementation results are reported.
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