Extending fault periodicity table for testing faults in memories under 20nm

著录项

• 来源
  《IEEE East-West Design Test Symposium》|2014年|1-4|共4页
• 会议地点
• 作者

  Harutyunyan G.; Shoukourian S.; Vardanian V.; Zorian Y.;

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• 原文格式 PDF
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• 关键词

  MOSFET circuits; built-in self test; integrated circuit reliability; integrated circuit testing; storage management chips; FPT; FinFET-based memories; fault periodicity table; fault sensitization complexity; fault testing; memory BIST infrastructure; memory faults; size 14 nm; size 16 nm; size 20 nm; test algorithms; Buildings; Built-in self-test; Complexity theory; FinFETs; Logic gates; Random access memory; FinFET; March test; built-in self-test; fault periodicity;

  机译：MOSFET电路;内置自检;集成电路可靠性;集成电路测试;存储管理芯片; FPT;基于FinFET的存储器;故障周期表;故障敏感度复杂度;故障测试;内存BIST基础设施;内存故障;尺寸为14 nm;尺寸16 nm;尺寸20 nm;测试算法;建筑物;内置自检;复杂性理论; FinFET;逻辑门;随机存取存储器; FinFET; 3月测试;内置自检;故障周期;