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首页> 外文会议>International Conference on Computer Communication and Informatics >Low Power Design of a Two Bit Mangitude Comparator for High Speed Operation
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Low Power Design of a Two Bit Mangitude Comparator for High Speed Operation

机译：用于高速工作的两位幅度比较器的低功耗设计

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摘要

Binary magnitude comparator is considered as an elementary apparatus in Arithmetic Logic Unit. Due to increased use of portable devices nowadays, energy efficient designs having less delay have become essential. This research introduces a new two-bit binary magnitude comparator consisting 46 transistors. To analyze performance, simulation of the proposed design has been conducted using Cadence Computer Aided Design apparatus in 90 nm Technology. To analyze design feasibility, the proposed design has been compared with the existing two-bit binary magnitude comparator design. According to simulation result, the proposed design displayed 9.865 μW average power consumption, 0.193 ns delay and 1.904 fJ Power Delay Product which was significantly less than the existing two-bit magnitude comparator designs.
机译：二进制幅度比较器被认为是算术逻辑单元中的基本装置。由于现在使用便携式设备的使用，所以具有较少延迟的节能设计成为必不可少的。本研究介绍了包括46个晶体管的新的两位二进制幅度比较器。为了分析性能，使用90nm技术的Cadence计算机辅助设计装置进行了仿真。为了分析设计可行性，所提出的设计已经与现有的两位二进制幅度比较器设计进行了比较。根据仿真结果，所提出的设计显示为9.865μW平均功耗，0.193 ns延迟和1.904 FJ功率延迟产品，其明显小于现有的两位幅度比较器设计。

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