Metrological definition and the target value of linewidth roughness (LWR) in gate pattern of MOSFETS are discussed. The effects of sampling interval of gate-LWR measurements using critical dimension scanning electron microscopy (CD-SEM) on the measurement accuracy was examined by both experiment and simulation. It was found that a 10-nm interval is sufficiently small to fully characterize roughness in a typically chosen 2-μm-long line with considering the LWR measurement error. Random image noise and intrinsic LWR variations are found to cause larger impacts on the measured value than the finiteness of the sampling interval. A practical procedure for improving the measurement accuracy is also discussed. Moreover, a methodology for establishing the gate-LWR target is proposed. Threshold-voltage shift caused by gate-LWR is given by using the LWR spectrum and the I-V curves of a transistor without LWR (ideal I-V curves). In order to calculate the target value, the ideal I-V curves, the typical gate width of the transistor and the tolerance for LWR-caused threshold-voltage variation are to be clarified.
展开▼
