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Analog Performance of Dynamic Threshold Voltage SOI MOSFET

机译:动态阈值电压SOI MOSFET的模拟性能

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This work presents the study of analog performance of Dynamic Threshold Voltage SOI MOSFET (DTMOS) devices compared to the conventional SOI MOSFET. The performance of DTMOS is analyzed by two-dimensional numerical simulations. When the gate voltage increases in DTMOS (body tied to gate), there is a body potential increase, which results in a higher drain current due to the sum of the MOS current with the bipolar transistor (BJT) one. Unfortunately, in this device is not possible to apply high gate voltage. High gate voltage (above 0.7 V) causes the source junction direct bias. The drain current increase is responsible for the transconductance over drain current improvement and contributes to the increase of the device intrinsic gain up to 15 dB for devices studied. The cut-off frequency is also improved.
机译:这项工作提出了与传统SOI MOSFET相比动态阈值电压SOI MOSFET(DTMOS)器件的模拟性能研究。通过二维数值模拟分析了DTMOS的性能。当DTMOS(与栅极相连的主体)中的栅极电压增加时,主体电位会增加,由于双极晶体管(BJT)的MOS电流之和,导致较高的漏极电流。不幸的是,在该器件中不可能施加高栅极电压。高栅极电压(高于0.7 V)导致源极结直接偏置。漏极电流的增加负责跨导过漏电流的改善,并有助于将所研究器件的器件固有增益提高到15 dB。截止频率也得到改善。

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