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3D Interconnect Technologies for Advanced MEMS/NEMS Applications

机译：适用于高级MEMS / NEMS应用的3D互连技术

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In the multi-chip module technology that became available in the early 1990s, several ICs are mounted side by side into a single ceramic package. Next, came the so-called System in a Package (SiP) technology in which ICs are stacked vertically, which reduces the footprint of a package dramatically. However, in a SiP system, there is no direct electrical interconnection between the different ICs. Instead, wire bonding is typically used to connect every IC individually to a common substrate. In recent years, a new technology referred to as 3D integration has been emerging, in which ICs are stacked vertically with direct electrical interconnects between each IC. The two key process technologies required for 3D integration are the fabrication of through silicon/substrate vias (TSVs) and chip-to-wafer or wafer-to-wafer bonding. The bonding provides a mechanical as well as an electrical interconnect between the different chips in the IC stack, while the TSVs provide the electrical interconnects through the chips themselves. Provided that potential yield and reliability issues are addressed, 3D integration offers the benefits of device miniaturization, improved performance, and reduced costs.
机译：在1990年代初开始使用的多芯片模块技术中，几个IC并排安装在一个陶瓷封装中。接下来，出现了所谓的系统级封装（SiP）技术，该技术将IC垂直堆叠，从而大大减少了封装的尺寸。但是，在SiP系统中，不同IC之间没有直接的电气互连。取而代之的是，通常使用引线键合将每个IC分别连接到一个公共基板上。近年来，出现了一种称为3D集成的新技术，其中将IC垂直堆叠，并在每个IC之间直接进行电气互连。 3D集成所需的两个关键工艺技术是硅/衬底通孔（TSV）的制造以及芯片到晶圆或晶圆到晶圆的键合。结合提供了IC堆栈中不同芯片之间的机械和电气互连，而TSV通过芯片本身提供了电气互连。如果解决了潜在的产量和可靠性问题，则3D集成可带来设备小型化，性能提高和成本降低的优势。

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