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Copper Plating for 3D Interconnects

机译:用于3D互连的镀铜

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摘要

Cu electroplating, as a technique used in metallization of through-Si vias (TSV) for 3D-stacked integrated circuits (3D-SIC), is required to provide not only a void-free TSV fill, but also short filling time and small overburden. The overburden, the thickness of the material deposited on the top surface of the wafer, has to be limited for compatibility with the chemical mechanical polishing (CMP). Since both Cu plating and CMP contribute significantly to overall 3D process cost, duration of these processes has to be minimized.
机译:作为用于3D堆叠集成电路(3D-SIC)的硅通孔(TSV)的金属化技术,需要进行铜电镀,以提供无空隙的TSV填充,而且填充时间短且覆盖层小。为了与化学机械抛光(CMP)兼容,必须限制覆盖层,即沉积在晶片顶面上的材料的厚度。由于铜电镀和CMP均对3D总体成本有重大贡献,因此必须将这些过程的持续时间最小化。

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