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Study on the curing process of no-flow and wafer level underfill for flip-chip applications.

机译：研究用于倒装芯片的非流动和晶圆级底部填充的固化工艺。

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摘要

Flip-chip is a first-level interconnect technology to connect the IC chip to the substrate. Underfill is an adhesion layer in between the IC chip and the substrate to enhance the reliability of the flip-chip package. The inventions of no-flow underfill and wafer level underfill increase the productivity and decrease the cost of flip-chip manufacturing. In order to fundamentally understand the curing process of the underfill in these two flip-chip processes, the study on the curing process of no-flow and wafer level underfill is proposed. Curing kinetic models are developed to describe the curing behavior of the underfills of different resin chemistry and reaction mechanisms. Based on the kinetic modeling, the degree of cure (DOC) of the underfill during the solder reflow process can be predicted. A 3-D transient thermal analysis model is built in ANSYS to understand the effect of underfill curing on the temperature distribution of a flip-chip package during the solder reflow process. The gelation behavior of different underfill materials is studied through experiments as well as Monte Carlo Simulations. The gelation of the underfill during the solder reflow process is predicted and confirmed by experiments. The B-stage properties of the wafer level underfill are studied and optimized. The assembly of the flip-chip with the wafer level underfill is demonstrated. The wafer warpage introduced by the underfill curing is modeled using finite element analysis and measured experimentally. The post cure behavior of the no-flow and wafer level underfill is investigated. The material properties of the underfill under different post cure conditions are monitored. In order to meet the reliability requirement for flip-chip package, inorganic fillers are indispensable to achieve low coefficient of thermal expansion and high modulus. Material and process innovations are explored to incorporate silica fillers into no-flow and wafer level underfill.
机译：倒装芯片是将IC芯片连接到基板的一级互连技术。底部填充是IC芯片和基板之间的粘合层，可增强倒装芯片封装的可靠性。无流动底部填充和晶圆级底部填充的发明提高了生产率，并降低了倒装芯片制造的成本。为了从根本上理解这两个倒装芯片工艺中底部填充胶的固化工艺，提出了无流动和晶圆级底部填充胶的固化工艺的研究。开发了固化动力学模型来描述不同树脂化学和反应机理的底部填充胶的固化行为。基于动力学模型，可以预测焊料回流过程中底部填充剂的固化程度（DOC）。 ANSYS内置了一个3-D瞬态热分析模型，以了解在焊料回流过程中底部填充固化对倒装芯片封装温度分布的影响。通过实验以及蒙特卡洛模拟研究了不同底部填充材料的胶凝行为。实验预测并确认了焊料回流过程中底部填充胶的凝胶化。研究并优化了晶圆级底部填充胶的B级特性。演示了倒装芯片与晶圆级底部填充的组装。由底部填充固化引入的晶片翘曲使用有限元分析进行建模，并通过实验进行测量。研究了无流动和晶圆级底部填充的后固化行为。监测在不同的后固化条件下底部填充材料的材料性能。为了满足倒装芯片封装的可靠性要求，无机填充剂对于实现低热膨胀系数和高模量是必不可少的。探索了材料和工艺方面的创新，以将二氧化硅填料加入无流动和晶圆级底部填充中。

著录项

  • 作者

    Zhang, Zhuqing.;

  • 作者单位

    Georgia Institute of Technology.;

  • 授予单位 Georgia Institute of Technology.;
  • 学科 Engineering Materials Science.; Chemistry Polymer.
  • 学位 Ph.D.
  • 年度 2003
  • 页码 289 p.
  • 总页数 289
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 工程材料学;高分子化学（高聚物）;
  • 关键词

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