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首页> 外文期刊>Advanced Functional Materials >Surface-Modified High-k Oxide Gate Dielectrics for Low-Voltage High-Performance Pentacene Thin-Film Transistors
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Surface-Modified High-k Oxide Gate Dielectrics for Low-Voltage High-Performance Pentacene Thin-Film Transistors

机译：用于低压高性能并五苯薄膜晶体管的表面改性高k氧化物栅极电介质

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摘要

In this study, pentacene thin-film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO_2-SiO_2 gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis-free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4-vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains: moreover, -OH groups on CeO_2-SiO_2 are terminated by C_6H_5, resulting in the formation of a more hydrophobic surface. Enhanced pentacene quality and reduced hysteresis is observed in current-voltage (Ⅰ-Ⅴ) measurements of the PVP-coated pentacene TFTs. Since grain boundaries and -OH groups are believed to act as electron traps, an OH-free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.
机译：在这项研究中，通过CeO_2-SiO_2栅极电介质的表面改性成功地制造了在低电压下具有高迁移率和低泄漏电流的并五苯薄膜晶体管（TFT）。栅极电介质的表面在确定并五苯TFT的性能和电气可靠性方面起着至关重要的作用。通过用适当的聚合物电介质钝化器件，可以获得几乎没有磁滞的晶体管。用聚（4-乙烯基苯酚）（PVP）涂覆后，表面粗糙度的降低导致形成均匀且大的并五苯晶粒：此外，CeO_2-SiO_2上的-OH基团被C_6H_5终止，导致形成更多的并五苯。疏水表面。在涂有PVP的并五苯TFT的电流-电压（Ⅰ-Ⅴ）测量中，可以发现并五苯的质量得到提高，磁滞减小。由于据信晶界和-OH基团起电子陷阱的作用，无OH且光滑的栅极电介质导致并五苯与栅极电介质之间的界面处的陷阱密度低。可以在低压下运行的电稳定器件的实现使OTFT成为未来柔性显示器和电子应用的极佳候选者。

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