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Crossing the Resolution Limit in Near-Infrared Imaging of Silicon Chips: Targeting 10-nm Node Technology

机译:硅芯片近红外成像的分辨率限制:靶向10-NM节点技术

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The best reported resolution in optical failure analysis of silicon chips is 120-nm half pitch demonstrated by Semicaps Private Limited, whereas the current and future industry requirement for 10-nm node technology is 100-nm half pitch. We show the first experimental evidence for resolution of features with 100-nm half pitch buried in silicon ( λ / 10.6 ), thus fulfilling the industry requirement. These results are obtained using near-infrared reflection-mode imaging using a solid immersion lens. The key novel feature of our approach is the choice of an appropriately sized collection pinhole. Although it is usually understood that, in general, resolution is improved by using the smallest pinhole consistent with an adequate signal level, it is found that in practice for silicon chips there is an optimum pinhole size, determined by the generation of induced currents in the sample. In failure analysis of silicon chips, nondestructive imaging is important to avoid disturbing the functionality of integrated circuits. High-resolution imaging techniques like SEM or TEM require the transistors to be exposed destructively. Optical microscopy techniques may be used, but silicon is opaque in the visible spectrum, mandating the use of near-infrared light and thus poor resolution in conventional optical microscopy. We expect our result to change the way semiconductor failure analysis is performed.
机译:硅芯片的光学故障分析中最佳报告的分辨率为120纳米半间距,通过SOMPAPS私人有限公司演示,而10nm节点技术的当前和未来的行业要求是100nm半间距。我们展示了第一个解决特征的第一个实验证据,其中埋藏在硅(λ/ 10.6)中埋藏的100纳米半间距,从而实现行业要求。使用使用固体浸渍透镜使用近红外反射模式成像获得这些结果。我们方法的关键新颖特征是选择适当大小的收集针孔。虽然通常理解,通常,通过使用具有足够信号电平的最小针孔来改善分辨率,发现在实践中,硅芯片存在最佳针孔尺寸,通过产生诱导电流的产生确定样本。在硅芯片的故障分析中,非破坏性成像对于避免扰乱集成电路的功能非常重要。 SEM或TEM等高分辨率成像技术要求晶体管破坏性地暴露。可以使用光学显微镜技术,但是硅在可见光谱中是不透明的,授权使用近红外光并因此在常规光学显微镜中的分辨率差。我们预计我们的结果更改了半导体故障分析的方式。

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