首页> 外文期刊>Japanese Journal of Applied Physics. Part 1, Regular Papers, Brief Communications & Review Papers >Fabrication and Characterization of Ferroelectric Gate Field-Effect Transistor Memory Based on Ferroelectric-Insulator Interface Conduction
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Fabrication and Characterization of Ferroelectric Gate Field-Effect Transistor Memory Based on Ferroelectric-Insulator Interface Conduction

机译:基于铁电-绝缘子界面导电的铁电栅场效应晶体管存储器的制作与表征

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摘要

A new type of ferroelectric gate field-effect transistor (FET) using ferroelectric-insulator interface conduction has been proposed. Drain current flows along the interface between the ferroelectric and insulator layers and requires no semiconductor. The channel region of the FET is composed of a Pt/insulator HfO_2/ferroelectric Pb(Zr_(0.52)Ti_(0.48))O_3 (PZT)/Pt/TiO_2/SiO_2/Si multilayer, and the source and drain areas are formed at the interface of the PZT and HfO_2 films. Drain current versus gate voltage characteristics show a clockwise hysteresis loop similar to that for a conventional p-channel transistor. The FET shows that the on/off ratio of the conduction current is within 10~5 to 10~6 and that the off-state current is about 10~(-10) A.
机译:提出了一种利用铁电-绝缘体界面导电的新型铁电栅场效应晶体管(FET)。漏极电流沿着铁电层和绝缘层之间的界面流动,不需要半导体。 FET的沟道区由Pt /绝缘体HfO_2 /铁电Pb(Zr_(0.52)Ti_(0.48))O_3(PZT)/ Pt / TiO_2 / SiO_2 / Si多层组成,并且在PZT和HfO_2膜的界面。漏极电流与栅极电压的关系曲线显示出类似于常规p沟道晶体管的顺时针磁滞回线。 FET显示传导电流的导通/截止比在10〜5至10〜6之内,截止状态电流约为10〜(-10)A.

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