A fully integrated CMOS phase-locked loop with 30 MHz to 2 GHz locking range and ±35 ps jitter

Chao Xu; Winslow Sargeant; Kenneth R. Laker; Jan Van Der Spiegel

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A fully integrated CMOS phase-locked loop with 30 MHz to 2 GHz locking range and ±35 ps jitter

机译：具有30 MHz至2 GHz锁定范围和±35 ps抖动的完全集成CMOS锁相环

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A fully integrated phase-locked loop (PLL) fabricated in a 0.24 μm, 2.5 v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30 MHz up to 2 GHz in 0.24 μm CMOS technologies. Also it has very low peak-to-peak jitter less than ±35 ps at 1.25 GHz output frequency.

机译：描述了采用0.24μm，2.5 v数字CMOS技术制造的完全集成的锁相环（PLL）。 PLL旨在用于光纤通信芯片中的每秒数千兆位的时钟恢复电路中。该PLL首次实现了非常大的锁定范围，在0.24μmCMOS技术中该锁定范围从30 MHz到2 GHz。它还具有非常低的峰峰值抖动，在1.25 GHz输出频率下小于±35 ps。

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来源
《Analog Integrated Circuits and Signal Processing》 |2003年第2期|共7页
作者
Chao Xu; Winslow Sargeant; Kenneth R. Laker; Jan Van Der Spiegel;
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原文格式 PDF
正文语种 eng
中图分类半导体集成电路（固体电路）;
关键词
Phase-locked loop (PLL); Clock data recovery; Dual loop architecture; Jitter;

机译：锁相环（PLL）;时钟数据恢复;双环架构;抖动;

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专利

1. A fully integrated CMOS phase-locked loop with 30 MHz to 2 GHz locking range and ±35 ps jitter [J] . Chao Xu, Winslow Sargeant, Kenneth R. Laker, Analog Integrated Circuits and Signal Processing . 2003,第1a2期

机译：具有30 MHz至2 GHz锁定范围和±35 ps抖动的完全集成CMOS锁相环
2. A 4224 MHz low jitter phase-locked loop in 0.13-um CMOS technology [J] . Chen Hu, Lu Bo, Shao Ke, Journal of Semiconductors . 2010,第1期

机译：采用0.13um CMOS技术的4224 MHz低抖动锁相环
3. A 4224 MHz low jitter phase-locked loop in 0.13-um CMOS technology [J] . Chen Hu, Lu Bo, Shao Ke, Journal of Semiconductors . 2010,第1期

机译：采用0.13um CMOS技术的4224 MHz低抖动锁相环
4. Fully integrated CMOS phase-locked loop with 30 MHz to 2 GHz locking range and 35 ps jitter [C] . Chao Xu, Sargeant, W., Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on . 2001

机译：具有30 MHz至2 GHz锁定范围和35 ps抖动的完全集成CMOS锁相环
5. A fully integrated 1.8GHz CMOS phase-locked loop [D] . Zhang, Frank 2001

机译：完全集成的1.8GHz CMOS锁相环
6. Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications [O] . Bilal I. Abdulrazzaq, Omar J. Ibrahim, Shoji Kawahito, 2016

机译：具有可调范围CMOS延迟锁定环路的亚皮秒抖动设计适用于高速和低功耗应用
7. Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and +-35ps Jitter [O] . Chao Xu, Winslow Sargeant, Kenneth R. Laker, 2015

机译：完全集成的CmOs锁相环，具有30mHz至2GHz的锁定范围和+ 35ps的抖动
8. 350 MHz Bipolar Monolithic PLL (Phase-Locked Loop) [R] . Soyuer, M., Meyer, R. G. 1988

机译：350 mHz双极单片pLL（锁相环）

A fully integrated CMOS phase-locked loop with 30 MHz to 2 GHz locking range and ±35 ps jitter

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