• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>Parallel Processing Letters >HMC-SIM: A Simulation Framework for Hybrid Memory Cube Devices
【24h】

HMC-SIM: A Simulation Framework for Hybrid Memory Cube Devices

机译：HMC-SIM：混合内存多维数据集设备的仿真框架

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

The recent advent of stacked die memory and logic technologies has lead to a resurgence in research associated with fundamental architectural techniques. Many architecture research projects begin with ample simulation of the target theoretical functions and approach. However, the logical and physical nature three-dimensional stacked devices, such as the Hybrid Memory Cube (HMC) specification, fundamentally do not align with traditional memory simulation techniques. As such, there currently exists a chasm in the capabilities of modern architectural simulation frameworks. This work introduces a new simulation framework developed specifically for the Hybrid Memory Cube specification. We present a set of novel techniques implemented on an associated development frame- work that provide an infrastructure to exibly simulate one or more Hybrid Memory Cube stacked die memory devices attached to an arbitrary core processor. The goal of this development infrastructure is to provide architectural simulation frameworks the ability to begin migrating current banked DRAM memory models to stacked HMC-based designs without a reduction in simulation fidelity or functionality. In addition to the core architecture, this work also presents a series of memory workload test results that represent unit stride and random access memory patterns using the HMC-Sim infrastructure. These evaluations confirm that HMC-Sim can provide insightful guidance in designing and developing highly efficient systems, algorithms, and applications, considering the next-generation three-dimensional stacked memory devices.
机译：堆叠式裸片存储器和逻辑技术的最新出现导致与基础架构技术相关的研究重新流行。许多建筑研究项目从对目标理论功能和方法的充分模拟开始。但是，三维混合堆栈的逻辑和物理性质（例如混合内存多维数据集（HMC）规范）从根本上与传统的内存模拟技术不符。因此，现代建筑仿真框架的功能目前存在鸿沟。这项工作介绍了一个专门为混合内存多维数据集规范开发的新仿真框架。我们提出了一套在相关的开发框架上实施的新颖技术，这些技术提供了可灵活模拟连接到任意核心处理器的一个或多个混合内存多维数据集堆叠式裸片存储设备的基础架构。此开发基础结构的目标是为体系结构仿真框架提供开始将当前存储的DRAM内存模型迁移到基于HMC的堆叠设计的能力，而不会降低仿真保真度或功能。除了核心体系结构之外，这项工作还提出了一系列内存工作负载测试结果，这些结果代表使用HMC-Sim基础架构的单元步幅和随机访问内存模式。这些评估证明，考虑到下一代三维堆叠存储设备，HMC-Sim可以为设计和开发高效的系统，算法和应用程序提供有见地的指导。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号