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HMC CONTROL DEVICE AND METHOD OF CPU SIDE AND HMC SIDE FOR LOW POWER MODE, AND POWER MANAGEMENT METHOD OF HMC CONTROL DEVICE
HMC CONTROL DEVICE AND METHOD OF CPU SIDE AND HMC SIDE FOR LOW POWER MODE, AND POWER MANAGEMENT METHOD OF HMC CONTROL DEVICE
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机译：低功耗模式下的hmc控制装置，cpu侧和hmc侧的方法以及hmc控制装置的电源管理方法
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摘要
Disclosed are an HMC control device and method of a CPU side and an HMC side for a low power mode, and a recording medium related thereto. The disclosed HMC control device of a CPU side comprises: a link master for storing request packets of a CPU in a request buffer and transmitting the same to the HMC control device of an HMC side in the stored order; and a plurality of link parts each including a link slave for storing the request packets received from the HMC control device of an HMC side in a response buffer and transmitting the same to the CPU in the stored order, wherein: when a request for the low power mode of the CPU occurs, the link master is switched to a standby mode in which the request packets of the CPU are no longer received; only when the link master checks in the standby mode that the buffer is empty, the link master generates a check packet and transmits the same to the HMC control device of an HMC side; and when the link slave receives the check packet from the HMC control device of an HMC side, the link master is switched to a sleep mode. According to the disclosed device, the loss of packets does not occur and switching to a low power mode can be stably performed.
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