Ultra-low voltage and high speed NP domino carry propagation chain

机译：超低压高速NP多米诺骨牌传播链

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In this paper, an Ultra Low Voltage NP domino logic style is presented to perform a 32 bit computation in a carry propagation chain. The presented logic style is targeted to operate at the supply voltages near the sub-threshold regime. Simulated results of 32-bit proposed carry chain compared to the conventional carry chain conclude that the proposed approach offers a superb improvement in terms of speed and EDP. The proposed carry chain has a relative delay and EDP of only 2.68% and 8% respectively compared to the conventional carry chain. The 32-bit ULV NP domino carry chain using 90nm TSMC CMOS process technology with a supply voltage of 300mV could be operated at a clock frequency of 50MHz.

机译：在本文中，提出了一种超低压NP多米诺骨牌逻辑样式，以在进位传播链中执行32位计算。提出的逻辑风格旨在在亚阈值范围附近的电源电压下工作。与传统进位链相比，32位提议的进位链的仿真结果得出结论，该提议的方法在速度和EDP方面提供了极好的改进。与常规进位链相比，提出的进位链的相对延迟和EDP分别仅为2.68％和8％。使用90nm TSMC CMOS工艺技术，电源电压为300mV的32位ULV NP多米诺骨牌运载链可以在50MHz的时钟频率下运行。

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《2013 IEEE Faible Tension Faible Consommation》|2013年|1-4|共4页
会议地点 Paris(FR)
作者
Mahmood; Sohail Musa; Berg; Yngvar;
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University of Oslo Department of Informatics Oslo, Norwayc;

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正文语种 eng
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机译：用于超低电源电压的高速数字Domino逻辑
2. Circuit improvements for high-speed domino logic: for the Manchester carry chain [J] . Blair G.M. Electronics Letters . 1998,第3期

机译：高速多米诺逻辑的电路改进：曼彻斯特进位链
3. NP-Domino, Ultra-Low-Voltage, High-Speed, Dual-Rail, CMOS NOR Gates [J] . Ali Dadashi, Omid Mirmotahari, Yngvar Berg Circuits and Systems . 2016,第8期

机译：NP-Domino，超低压，高速，双轨，CMOS NOR门
4. Ultra-low voltage and high speed NP domino carry propagation chain [C] . Mahmood, Sohail Musa, Berg, IEEE Faible Tension Faible Consommation . 2013

机译：超低电压和高速NP Domino携带传播链
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7. Implementation of high speed low power carry look ahead adder using Domino logic [O] . Mousam Halder 2014

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Ultra-low voltage and high speed NP domino carry propagation chain

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