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首页> 外文会议>2017 29th International Symposium on Power Semiconductor Devices and IC's >Process design of superjunction MOSFETs for high drain current capability and low on-resistance
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Process design of superjunction MOSFETs for high drain current capability and low on-resistance

机译：具有高漏极电流能力和低导通电阻的超结MOSFET的工艺设计

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摘要

This paper reports that the process design to cope with both high drain current density and low on-resistance in the superjunction (SJ) MOSFET. The SJ structure is attractive to reduce the specific on-resistance dramatically due to the charge compensation concept. The drain saturation current density, however, is limited by JFET depletion at bottom region of the SJ structure. This is an obstacle to shrink the chip area due to low drain current capability, even if the on-resistance can be reduced by the lateral SJ pitch narrowing. Since the SJ structure depletion is determined by the column active doping density, the SJ process design strongly affects the saturation current density and the on-resistance. The process margin cut and high doping efficiency are key factors for the compatibility between the increase of saturation drain current density and the on-resistance reduction in SJ-MOSFET.
机译：本文报道了在超级结（SJ）MOSFET中要同时满足高漏极电流密度和低导通电阻的工艺设计。由于电荷补偿的概念，SJ结构具有显着降低比导通电阻的吸引力。然而，漏极饱和电流密度受到SJ结构底部区域JFET耗尽的限制。即使通过横向SJ间距变窄可以减小导通电阻，这也是由于低漏极电流能力而导致缩小芯片面积的障碍。由于SJ结构的损耗由列有源掺杂密度决定，因此SJ工艺设计会严重影响饱和电流密度和导通电阻。工艺裕量的降低和高掺杂效率是SJ-MOSFET中饱和漏极电流密度的增加与导通电阻降低之间兼容性的关键因素。

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